JPS60160236A - Synchronism system of pcm multiplex converter - Google Patents

Abstract

PURPOSE:To execute stably and economically ultrahigh speed synchronism by shifting a high order group clock by 1 bit when a signal of synchronism establishment is not obtained even if a prescribed synchronism restoration time is elapsed from a synchronism circuit detecting a synchronism bit existing in a PCM signal for the establishment of synchronism. CONSTITUTION:When a data is given to a shift register 1 from a channel 1' in order, the channel 1' is stored in a register 2, a channel 2' is stored in a register 3 and a channel 3' is stored in a register 4 respectively. Thus, since a synchronism circuit 7 cannot detect a synchronism bit F, an out of synchronism signal is transmitted to a timer 8. Since the signal for establishing synchronism is not obtained regardless of the elapse of the synchronism restoration time, the timer 8 activates a 1-bit shifter 5 so as to shift the high order group clock by one bit. Then the synchronism locking of the synchronism circuit 7 is conducted again. Since the synchronism circuit 7 cannot establish the synchronism in this case, the timer 8 activates the 1-bit shifter 5 so as to shift the high order group clock by one bit. Since the synchronism bit F is stored in the register 2 this time, the synchronism circuit 7 establishes the synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a PCM multiplex converter, and more particularly to a synchronization system for a PCM multiplex converter that can stably and economically perform ultra-high-speed synchronization.

(b) Prior art and problems Since the PCM multiplex converter needs to use a clock synchronized with the bit period of the transmitted PCM signal,
A PC receives the clock used within the device using a synchronization circuit.
Synchronized with M signal.

It is also determined whether synchronization is achieved with the synchronization pulse of the received PCM signal. In the conventional synchronization method, synchronization is determined within a pulse width of 1 bit, and when the degree of multiplexing of PCM signals becomes large and an ultra-high speed synchronization circuit is required, the conventional method is not suitable. That is, the width of one bit has become extremely narrow, and since it is necessary to operate at ultra-high speed, it has become difficult to realize it due to limitations in device configuration, component performance, etc.

(C) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks by establishing synchronization in a low-order group to reduce the operating speed, and to create a stable and economical PCM multiplexing device with small hardware. The purpose is to provide a synchronization method.

(d) Structure of the Invention The structure of the present invention is a PCM multiplex conversion device that establishes synchronization using a predetermined low-order group channel, and includes means for shifting a high-order group clock one bit at a time, and a high-order group clock received from the shifting means. means for dividing the clock into N channels; means for shifting the PCM signal converted into a higher order group every l channel by the higher order group clock; and the frequency dividing means for shifting the signal for each channel shifted by the shifting means. A synchronization circuit that detects synchronization bits present in the PCM signal and establishes synchronization receives a synchronization establishment signal even after a predetermined synchronization recovery time has elapsed. If it cannot be obtained, the higher-order group clock is shifted by one bit.

(e) Embodiment of the invention FIG. 1 is a block diagram of a circuit showing an embodiment of the invention.
FIG. 2 is a time chart explaining the operation of FIG. 1. This embodiment shows a case where three channels of a low-order group are multiple-converted to form a high-order group.

A PCM signal of a multiplexed high-order group as shown in the frame of FIG. 3 enters the shift register 1 from the terminal A. Also terminal B
A high-order group clock enters from , shifts the shift register 1, passes through the 1-bit shifter 5, and enters the 1/3 frequency divider 6. Register 2.3.4 takes in the output of shift register 1 every three clocks by the output of 1/3 frequency divider 6. Therefore, for example, if the synchronization bit F at the beginning of a frame is taken into register 2, the channel bit is stored in register 3, and the channel ■ is sequentially stored in register 4. At the next clock, channel 2 is stored in register 2, channel 2 is stored in register 3, and channel 2 is stored in register 4.

Therefore, the terminal φ1 has a synchronization bit F as shown in FIG. 3 φ1.
, Channel■.

Channel ■ is sent out continuously, and channel ■, channel ■, channel ■ are sent out continuously to terminal φ2, and terminal φ3 is sent out continuously as channel ■, channel ■, channel ■.
Channel ■, Channel ■, Channel ■ are continuously transmitted. In this case, since the synchronization circuit 7 can detect the synchronization bit F, synchronization can be established. If shift register l is entered in order from channel ■, channel ■ will be stored in register 2, and channel ■ will be stored in register 3.
However, in the register 4, channels (2) are stored respectively. Therefore, since the synchronization circuit 7 cannot detect the synchronization bit F, it sends an out-of-synchronization signal to the timer 8. Timer 8 is set to 1 because no synchronization establishment signal is obtained even after the specified synchronization recovery time has elapsed.
The bit shifter 5 is operated to shift the high-order group clock by one bit. Therefore, registers 2, 3.4 are channels ■
, Channel■.

Shift each channel by one channel and import. Then, the synchronization pull-in operation of the synchronization circuit 7 is performed again. In this case as well, the synchronization circuit 7 cannot establish synchronization, so the timer 8 operates the 1-bit shifter 5 to shift the high-order group clock by 1 bit.

This time, the synchronization bit F is stored in the register 2, so the synchronization circuit 7 establishes synchronization. Therefore, if synchronization is not established, the synchronization bit F can always be found by performing the same operation twice at most as described above.

If the number of low-order group channels is N, the 1/3 frequency divider 6 is set to 1.
/H frequency divider, N registers 2 and 3.4, and shift register 1 is also an N-bit shift register.

(f) As described in detail, the present invention reduces the operating speed of the synchronous circuit to 1/H.
It is possible to provide a stable and economical synchronization method.

[Brief Description of the Drawings] Figure 1 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 2 is a time chart explaining the operation of FIG. 1. 1 is a shift register, 2, 3.4 are registers, 5 is a 1-bit shifter, 6 is a 1/3 frequency divider, 7 is a synchronization circuit, and 8 is a timer.

Claims (1)

[Claims] P that establishes synchronization using a predetermined low-order group channel
The CM multiplex conversion device includes means for shifting a high-order group clock one bit at a time, means for frequency-dividing the high-order group clock received from the shifting means into N channels, and converting the PCM signal converted into the high-order group into one channel using the high-order group clock. and means for temporarily storing the signals for each channel shifted by the shifting means in the shift order at the timing when the frequency is divided by the frequency dividing means,
If a synchronization circuit that detects a synchronization bit present in the PCM signal and establishes synchronization does not obtain a synchronization establishment signal even after a predetermined synchronization restoration time has elapsed, the high-order group clock is shifted by one bit. A synchronization method for PCM multiplex conversion equipment.