RU1811006C - Serial-to-parallel code translator - Google Patents

Abstract

The invention relates to computer technology and can be used in digital data transmission systems. In the invention, due to a single clocking of all stages of the converter, an increase in its speed is achieved. The serial to parallel converter contains m stages 1 (t 1, N), each of which contains n 2k conversion nodes 2 (k .1, m), and a synchronization trigger 6. Each conversion unit 2 contains triggers 3, 4, and 5. 2 il.

Description

The invention relates to computing and may find application in digital data transmission channels.

The aim of the invention is to increase the speed of the converter by a single clocking of all stages.

In FIG. 1 is a block diagram of a converter; in FIG. 2 are timing diagrams illustrating the operation of the converter.

The serial to parallel converter contains m stages

1 (m iTKi), each of which contains n 2k 1 transformation nodes 2 (k 1, m), each transformation node 2 contains triggers 3, 4 and 5, each stage 1 contains a synchronization trigger b.

In FIG. 1, the numbers 7 and 8 are indicated by the information input and the synchronization input of the converter, respectively, by the numbers 9 and 10, respectively, the information outputs and the output of the signal from the end of the conversion of the converter.

The device operates as follows.

A sequence of input data (Fig. 2a) is supplied simultaneously to the inputs of the first and second triggers 3 and 4 to record information of the first conversion stage 1.1. The clock signal accompanying the data (Fig. 2 b) is supplied to the input of the trigger 6.1 of the counter of the same stage. The data recording in the first and second triggers 3,4 is controlled sequentially: in the first cycle, the recording is made in the first trigger 3, to which the third trigger 5 is connected, by the positive edge of the signal (Fig. 2 c) from the second output of trigger 6.1; in the next step, to the second trigger 4, with a positive edge of the signal (Fig. 2 g) from the first output of the same trigger 6. The same signal (Fig. 2 g) overwrites the information from the first trigger 3 to record information in the third trigger 5. Thus Thus, in the second clock, the information contained in two consecutive time clocks of the input data (Fig. 2, a) appears at the outputs of the node 2.1 (Fig. 2 e, g), and the frequency of the triggers 3, 4 for recording information (FIG. 2 d, g) and delay trigger 5 (FIG.

2f) of the node 2.1 of the first stage 1.1 is half the frequency of the input data (Fig. 2a).

Since all elements of the circuit are triggers 3, 4 for recording information, triggers 5

delays and triggers 6 are identical, then the delay times of the input information and the synchronization signal are the same. Synchronization of the output from each

the conversion stage and the synchronization signal of the corresponding trigger 6 provides the ability to connect all elements of the circuit without additional phasing of the signals in time. At the same time, in each subsequent cascade, the double output bit size of the parallel output data is doubled, while the information change frequency is halved and the data synchronization and synchronization signal are kept ..

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SUMMARY OF THE INVENTION A serial to parallel code converter containing in each of m stages (t 1, N) n 2k 1 conversion nodes (k 1, t) performed on the first and second triggers, the data inputs of which are combined, the data input of the first trigger of the node the conversion of the first stage is an information input of the converter, characterized in that, in order to increase the speed of the converter due to a single clocking of all stages, a synchronization trigger is introduced into each stage and a third node in each conversion node trigger, in each conversion node the output of the first trigger is connected to the data input of the third trigger, in each stage the first output of the synchronization trigger is connected to the sync inputs of the second and third triggers of the conversion nodes, the second output of the synchronization trigger is connected to the clocks of the first triggers of the conversion nodes of this stage and to the trigger input synchronization of the subsequent stage, the output of the synchronization trigger of the last stage is the output of the signal from the end of the converter conversion, the outputs of the second and retih triggers converting each node of each stage, except the last, coupled to the data inputs of the first flip-flops corresponding to the nodes of the succeeding stage conversion outputs of the second and third flip-flops of the last stage conversion nodes are data outputs of the transducer, the synchronization trigger input of the first stage is input to the synchronization transducer.

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