JPH0568013A - Digital signal multiplex communication system - Google Patents

Abstract

PURPOSE:To reduce the cost by making the synchronous signal of low-order data in an optional channel different from that of other channel at a transmission side and realizing multiplexing/demultiplexing with simple configuration. CONSTITUTION:The transmission side is provided with a high-order synchronous signal generating means which selects an optical low-order encoder among N-channels of encoders and allows the encoder to generate low-order data CH1-CH12 having the synchronous signal of a different pattern from that of other channels and uses the synchronous signal of the different pattern for the frame synchronizing signal of high-degree data. Moreover, a reception side is provided with a synchronous signal detecting means detecting the synchronous signal of the different pattern and with a channel adjusting means adjusting the demultiplexed output channel of a multiplexer/demultiplexer 7 based on the detection timing of the detection means and making the channel of the low-order encoder coincident with that of low-order decodes 81-81. Thus, it is not required for the multiplexer to generate a high-order synchronous signal newly and to add the synchronous signal to multiplexed data. Thus, the configuration is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal multiplex communication system for multiplexing and transmitting, for example, digitized voice signals.

[0002]

2. Description of the Related Art Conventionally, when a plurality of digital data are multiplexed and transmitted, a transmitting side adds a frame synchronization code to the multiplexed high-order digital data and transmits it, and a receiving side transmits the frame synchronization code. A method of detecting and separating this into low-order digital data is used as a reference timing. 2.048Mb / currently used in satellite broadcasting
The contents will be described by taking as an example a system that multiplexes 12 channels of s digital voice and transmits it.

FIG. 6 shows the system configuration. On the transmission side, the audio signal of each channel is PCM-encoded inside the low-order encoders 11 to 112, and then encoded into low-order data in the format shown in FIG. 7A. These low-order data are sent from the low-order encoders 11 to 112 to the multiplexing device 2 in the order shown in FIG. The frame structure of the transmitted low-order data is shown in FIG. 7 (b). A synchronization code (16 bits) is added to this low-order data in advance so that the PCM decoder LSI used in the satellite broadcast receiver can be used as it is as a low-order decoder.

The multiplexer 2 multiplexes the input 12-channel low-order data bit by bit to obtain high-order data (2.048 Mb / s × 12 CH = 24.576 Mb /
s) is generated. In this case, if the low-order data of each channel is simply multiplexed in bit units, the synchronization pattern of low-order data is the same in each channel as shown in FIG. Become.

If this pattern is used as it is as a synchronization code for high-order data, the synchronization code length is 16 bits × 12.
Channel = 192 bits, which is extremely long, which is not preferable in terms of transmission efficiency. Therefore, in the conventional case,
16 bits out of 92 bits are used as a synchronization code for multiplexed data, and the remaining 192-16 = 176 bits are used for other purposes. FIG. 9 shows the format of high-order data.

FIG. 10 shows a concrete structure of the multiplexer 2. The high-order clock generator 21 is 2.048M.
A high-order clock of Hz × 12CH = 24.576 MHz is generated. This clock is 1/12 in the first frequency divider 22.
To a low order clock of 2.048 MHz. This low-order clock is further divided into 1/2048 by the second frequency divider 23, whereby a frame pulse (1 kHz) is generated. These low-order clocks and frame pulses are transmitted to the low-order encoders 11 to 11 respectively.
It is sent to 112 and used for generation of low-order data.

On the other hand, the P / S (parallel input / serial output) shift register 24, based on the low-order clock obtained by the first frequency divider 22, outputs the low-order data C of each channel.
It operates as a bit unit multiplexing circuit that inputs H1 to CH12 in parallel at a speed of 2048 MHz and serially outputs these at a speed of 12 times based on a high-order clock. The output data format of this shift register 24 is shown in FIG.
It is the same as the format shown in.

Therefore, the high-order synchronization code generator 25 generates a 16-bit high-order synchronization code based on the high-order clock every time the output pulse of the second frequency divider 23 is input. This high-order synchronization code is sent to the 3-input 1-output multiplexer 27 together with the parallel data of the P / S shift register 24 and the output data of the high-order independent data generator 26.

The switching control of the multiplexer 27 is performed by the switching control signal from the switching controller 28. This switching control signal is generated, for example, by counting a predetermined number of high-order clocks. As a result, from the multiplexer 27, the higher-order synchronization code is derived in the period a of FIG. 9, the higher-order independent data is derived in the period b, and the multiplexed data is derived in the period c. Higher-order data in the format shown in 9 will be output. As shown in FIG. 6, the high-order data generated in this way becomes a transmission signal through the modulator / transmitter 3, and is transmitted from the transmission antenna 4.

On the other hand, on the receiving side, the received signal obtained by the receiving antenna 5 is returned to the original higher order data via the receiver / demodulator 6 and supplied to the demultiplexing device 7. The format of the high-order data supplied to this demultiplexer 7 is the same as the output of the multiplexer 2 on the transmission side (higher-order data configured in the format shown in FIG. 9). Further, the high-order clock for reproducing the high-order data is extracted and reproduced from the received signal by the clock reproduction circuit arranged inside the demodulator,
It is supplied to the demultiplexer 7.

FIG. 11 shows a specific configuration of the demultiplexing device 7. The high-order synchronization code detector 71 detects the high-order synchronization code arranged at the beginning of the frame format from the input high-order data based on the high-order clock, and supplies the detection timing to the frame synchronization pulse generator 72, A frame pulse synchronized with the frame timing of higher order data is generated. This frame pulse is a 1/12 divider 7
3 reset signal. That is, this 1
As shown in FIG. 12, the / 12 frequency divider 73 generates a low-order clock completely synchronized with the low-order data phase in the high-order data.

On the other hand, the high-order data is supplied to the S / P (serial input / parallel output) shift register 74. The S / P shift register 74 inputs the high-order data in parallel based on the high-order clock, and outputs the parallel data in 12 series in bit units based on the low-order clock generated by the 1/12 frequency divider 73. That is, since the low-order clock is used as the parallel output timing of the shift register 74, the parallel output terminal number of the shift register 74 and the low-order channel number have a one-to-one correspondence. That is, C
The low-order data of CH1 is output to the output terminal of H1.

In the output data format of the shift register 74 at this time, as shown in FIG. 13, the first bit at the beginning is a part of the higher-order synchronization code, the following 15 bits are higher-order independent data, and the 17th to 2048th bits. Up to bits are the outputs of the low-order encoders 11 to 112 on the transmission side.
The low-order decoders 81 to 812 in the next stage are the low-order encoder 11
Since they are designed to be used in pairs with .about.112, even if the data of the format shown in FIG. 13 is directly supplied to the low order decoders 81 to 812, low order frame synchronous reproduction cannot be performed.

For this reason, as shown in FIG. 11, low-order decoder interface circuits 751 to 7512 are added to the output stage of the demultiplexer 7 for each channel. These interface circuits 751 to 751
2 includes a low-order synchronization code generator A, a 2-input 1-output multiplexer B, and a switching controller C for switching and controlling the multiplexer B.

The low-order sync code generator A is a 1/12 frequency divider 7
The low-order synchronization code is generated at the low-order clock timing from 3. The switching controller C is based on the high-order clock, and
The multiplexer B is switch-controlled so as to derive the low-order synchronization code during the period d of 3 and derive the separated data during the period e. As a result, low-order data in the format shown in FIG. 7 is obtained in each channel, and the low-order data shown in FIG.
Of low order decoders 81 to 812.

However, in the conventional digital signal multiplex communication system having the above-mentioned configuration, the transmitting side removes the low-order synchronization code part from the low-order synchronization signal and newly adds the high-order synchronization code, so that the multiplexing is performed. The apparatus requires a high-order synchronous code generator, a switch (multiplexer), and a switch controller. Further, on the receiving side, since the high-order sync code part and the high-order independent data part in the high-order sync signal are removed and a new low-order sync code is newly added, the low-order decoder interface circuit is low in the demultiplexer. Only the number of next channels is required, which makes the entire system complicated and expensive. In particular, in a communication system such as a satellite communication network having an extremely large number of receiving stations, the cost increase of the receiving stations directly leads to the cost increase of the system, which is not preferable.

[0017]

As described above, in the conventional digital signal multiplex communication system, the transmitting side removes the low-order synchronization code part in the low-order synchronization signal and multiplexes a new high-order synchronization code. A device for adding the next-order synchronization code is required, and the receiving side removes the higher-order synchronization code part and the higher-order independent data part in the higher-order synchronization signal at the time of demultiplexing, and newly creates a lower-order synchronization code. A device for adding is required for a low number of channels, which makes the whole complicated and expensive.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide a digital signal multiplex communication system capable of realizing multiplexing and demultiplexing with a simple structure and thereby reducing costs. To aim.

[0019]

In order to achieve the above object, the present invention provides

On the transmitting side, N (N is a natural number) low-order encoders for generating low-order data of the same format each having a synchronization signal from a transmitted digital signal, and low-order encoders generated by these low-order encoders. A multiplexing device for sequentially multiplexing the data bit by bit to generate high-order data and a transmission means for transmitting the high-order data generated by this device are provided, and the receiving side has the high-order data transmitted by the transmission means. Receiving means for receiving data, demultiplexing apparatus for demultiplexing high-order data obtained by this means into low-order data of N channels, and demultiplexing equipment provided respectively corresponding to the low-order encoders of N channels, In an N-channel low-order decoder for inputting low-order data separated by a separator and reproducing a digital signal, a digital signal multiplex communication system

The transmitting side selects any one of the N-channel low-order encoders to generate low-order data having a sync signal of a pattern different from those of the other channels, and to generate the low-order data of the different patterns. A high-order synchronization signal generation means for making a synchronization signal a frame synchronization signal of the high-order data,

The receiving side adjusts the demultiplexing output channel of the demultiplexing device based on the detection timing of the synchronizing signal detecting means for detecting the synchronizing signals of the different patterns, and the low order encoder and the low order decoder. And channel adjusting means for matching the channels of.

[0023]

In the digital signal multiplex communication system having the above structure, the synchronization signal in the low-order data of any one channel is made different from that of the other channel, and the synchronization signals of the different patterns are multiplexed to generate the higher-order data. Since the frame synchronizing signal is used, it is not necessary to newly generate a high-order synchronizing signal by the multiplexer and add it to the multiplexed data, which simplifies the structure of the multiplexer. Also, on the receiving side, the demultiplexing device can be adjusted because the demultiplexing output channels can be adjusted by detecting the synchronization signals of the different patterns.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. Here, a case where the present invention is applied to the system having the configuration shown in FIG. 6 will be described.

FIG. 1 shows a low-order encoder (1 in FIG. 6) on the transmission side.
1-112), 1a and 1b are A / A for converting L and R audio signals into digital signals, respectively.
It is a D (analog / digital) converter. The outputs of the A / D converters 1a and 1b are alternately derived by the first multiplexer 1c and sent to the second multiplexer 1d.

On the other hand, the low-order synchronization code generator 1e generates a low-order synchronization code based on the low-order frame pulse generated by the multiplexer 2 in the subsequent stage, but its code pattern is different only in the first channel CH1. Other channels CH1-C
H12 is set to be the same. This low-order synchronization code is supplied to the second multiplexer 1d. This second
The multiplexer 1d is switched and controlled by the switching controller 1f. The switching timing is determined, for example, by counting the low-order clocks generated by the multiplexer 2 in the subsequent stage, whereby the multiplexer 1d outputs low-order data in the format shown in FIG.

FIG. 2 shows the structure of the multiplexing device 2 on the transmission side. The high-order clock generator 2a is 2.048 MHz ×
It generates a high-order clock of 12CH = 24.576 MHz. This clock is divided into 1/12 by the first frequency divider 2b, whereby a low-order clock of 2.048 MHz is generated. This low-order clock is further used by the second frequency divider 2
It is divided by 1/2048 by c, and a low-order frame pulse (1 kHz) is generated by this. These low-order clocks and frame pulses are sent to the low-order encoders 11 to 112 of the respective channels and used for generating low-order data.

On the other hand, the P / S (parallel input / serial output) shift register 2d is provided with the low-order data C of each channel based on the low-order clock obtained by the first frequency divider 2b.
It operates as a bit-by-bit multiplexing circuit that inputs H1 to CH12 in parallel at a speed of 2.048 MHz and serially outputs these at a speed 12 times higher than that of a higher-order clock.

The output data format of the shift register 2d is different from the format shown in FIG. 8, and as shown in FIG. 3, every 12 bits in the first 12 × 16 = 192 bits is different from the other 11 bits. Different code patterns appear. This pattern matches the low-order sync code of the low-order encoder 11 of the first channel CH1, and the other 11-bit patterns are the second to twelfth channels CH2 to C.
It matches the low-order sync code patterns of the low-order encoders 12 to 112 of H12.

As can be seen by comparing FIG. 2 with FIG. 10, in this multiplexer 2, the high-order synchronous code generator, the multiplexer and the switching controller are omitted, and the shift register 2d is omitted.
Output data is sent as high-order data as it is.
FIG. 4 shows the structures of the demultiplexer 7 on the receiving side and the low-order decoders 81 to 812 of each channel.

First, in the demultiplexing device 7, the receiver /
The high-order data from the demodulator 6 is the S / P shift register 7a.
The high-order clock is supplied to the 1/12 frequency divider 7c via the OR gate circuit 7b. 1/12 frequency divider 7
c generates a low-order clock by dividing the high-order clock by 1/12. This low-order clock is supplied to the shift register 7a and the low-order decoders 81 to 812 of the respective channels. The shift register 7
a captures high-order data at the timing of the high-order clock, separates it into 12 channels, and outputs in parallel at the timing of the clock obtained by the 1/12 frequency divider 7c.

Next, the low-order decoder 81 of the first channel
In, the low-order data from the demultiplexer 7 is supplied to the decoder 8a and also to the low-order sync code detector 8b. When the low-order synchronization code detector 8b detects a preset code pattern from the low-order data, it outputs a synchronization detection state signal and generates a reset signal at the synchronization detection timing. The synchronization detection state signal is inverted by the inverting gate circuit 8c and then supplied to the AND gate circuit 8d. In the low-order decoders 82 to 812 of each channel except 81, the detection pattern of the low-order synchronization code detector 8b corresponds to the code pattern of the low-order encoders 12 to 112, and the pattern is different only in the first channel. ing.

On the other hand, the low-order clock from the demultiplexer 7 is divided by the 1/2048 frequency divider 8e by 1/2048 to become a bit clock. This bit clock is the decoder 8
a and is used for reading audio data, and 1
It is also supplied to the / 4 frequency divider 8f. The 1/2048 frequency divider 8e has its frequency division output timing initialized by a reset signal from the low-order synchronization code detector 8b.

The 1/4 frequency divider 8f performs forward protection and backward protection in order to protect the frame synchronization against data errors during transmission by the normal low-order synchronization code detection circuit. Is provided in order to monitor the frame synchronization state at regular intervals in consideration of the fact that it cannot be determined that the frame is out of synchronization. Although it is set to 1/4 here, the frequency division ratio may be changed according to the length of the front protection and the rear protection of the frame synchronization.

The output of the 1/4 frequency divider 8f is supplied to the AND gate circuit 8d. AND gate circuit 8d is 1 /
Bit clock divided by 4 (hereinafter, 1/4 clock)
And the sync detection state inversion signal are ANDed and the result is sent to the OR gate circuit 7b of the demultiplexing device 7. The audio data obtained by the decoder 8a is supplied to a D / A (digital / analog) converter 8g and converted into L and R audio signals.

By the way, in the demultiplexer 7 and the low order decoders 81 to 812 having the above-mentioned configuration, when the power is turned on,
From the uncertainty of the initial state of the 1/12 frequency divider 7c, S / P
There is no guarantee that the low-order data of the CH1 low-order encoder 11 will be output to the CH1 output terminal of the shift register 7a.

It is now assumed that low-order data for the CH3 low-order decoder 83 is available at the CH1 output terminal of the S / P shift register 7a. In this case, CH1 low order decoder 8
Since the sync code pattern of the low-order data supplied to 1 is different from the set pattern, sync detection cannot be performed. Therefore, the synchronization detection status signal becomes "0" and 1/20.
A reset signal is output to the 48-frequency divider 8e. Therefore, the output of the AND gate circuit 8d is once every four frames,
A pulse is obtained.

Since this pulse signal is applied to the OR gate circuit 7b of the demultiplexer 7, the 2.048 MHz clock output from the 1/12 frequency divider 7c is 1 in 4 frames.
Times, the phase advances by one clock with the high-order clock. Therefore, low-order data of CH2 is obtained at the CH1 output end of the S / P shift register 7a. Since the synchronization code pattern in the low-order data of CH2 is also different from that of CH1, the same operation described above is repeated, and finally the low-order data of CH1 is obtained at the output end of CH1 of the S / P shift register 7a. become.

At this point, the low-order sync code detector 8b of the CH1 low-order decoder 81 detects the sync code pattern, so that the sync detection state signal becomes "1", and a pulse is output to the output of the AND gate circuit 8d. It will not appear. as a result,
The output clock phase of the 1/12 divider 7c becomes constant,
CH1 low-order data can be continuously obtained at the CH1 output terminal of the S / P shift register 7a, and at the same time CH2
The low-order data of the corresponding channels can be obtained at the output ends of CH12.

Therefore, in the system having the above configuration, since the low-order synchronization code included in the low-order data is used for the synchronization detection of the demultiplexing circuit 7, the high-order multiplexer 2
It is possible to omit the addition of the high-order synchronization code, the detection of the high-order synchronization code and the addition of the low-order synchronization code in the high-order demultiplexing device 7, thereby simplifying the structure and reducing the cost.

The present invention is not limited to the above embodiment, and the demultiplexing device 7 may be constructed as shown in FIG. 5, for example. That is, in the demultiplexing device 7 shown in FIG. 4, the low-order synchronization code detector 8b of the CH1 low-order encoder 81 is used for synchronization detection of high-order data.
The demultiplexer 7 shown in FIG. 5 is characterized by detecting the low-order data synchronization code of CH1 (see FIG. 3) in the state of high-order data.

In FIG. 5, the high-order synchronization code detector 7d
Detects the low-order data synchronization code of CH1 arranged at the beginning of the frame format as the high-order synchronization code from the input high-order data based on the high-order clock, and supplies the detection timing to the frame synchronization pulse generator 7e. , Generates a frame pulse synchronized with the frame timing of higher order data. This frame pulse is a 1/12 divider 7
Used as a reset signal for f. The 1/12 frequency divider 7f generates a low-order clock completely synchronized with the low-order data phase in the high-order data.

On the other hand, the high-order data is supplied to the S / P shift register 7g. The S / P shift register 7g serially inputs high-order data based on a high-order clock and outputs 1
Based on the low-order clock generated by the / 12 frequency divider 7f, parallel output is performed in 12 units in bit units. At this time,
Since the low-order clock is used as the parallel output timing of the shift register 7g, the parallel output terminal number of the shift register 7g and the low-order channel number have a one-to-one correspondence. That is, the low-order data of CH1 is output to the output terminal of CH1.

The output of the shift register 7g at this time is
The format is already shown in FIG. 7 (b). Therefore, the output of each channel may be directly supplied to the low-order decoder having the conventional configuration without passing through the low-order decoder interface circuit. This embodiment is different from the embodiment of FIG. 5 described above in that it has a higher order synchronous code detector 7d.
However, signal feedback between the low-order decoder 81 and the demultiplexer 7 (AND gate circuit 8d in FIG. 4) is required.
Output) is unnecessary, and there is an advantage that timing adjustment during that time is unnecessary.

In each of the above embodiments, the case where the low-order synchronization code pattern of the low-order encoder 11 of CH1 is made different from the patterns of other channels has been described.
Even if the pattern of an arbitrary channel is made different from the patterns of other channels, the same operation can be performed. Other,
It goes without saying that various modifications can be made without departing from the scope of the present invention.

[0046]

As described above, according to the present invention, it is possible to provide a digital signal multiplex communication system capable of realizing multiplexing and demultiplexing with a simple structure and thereby reducing costs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a low-order encoder in an embodiment of a digital signal multiplex communication system according to the present invention.

FIG. 2 is a block diagram showing a configuration of a multiplexing device of the embodiment.

FIG. 3 is a diagram showing an output format of high-order data by the multiplexing device of the embodiment.

FIG. 4 is a block diagram showing the configurations of a demultiplexer and a low-order decoder of the same embodiment.

FIG. 5 is a block circuit diagram showing the configuration of a demultiplexer as another embodiment according to the present invention.

FIG. 6 is a block diagram showing an overall configuration of a digital signal multiplex communication system to which the present invention is applied.

FIG. 7 is a diagram showing an output format of low-order data in the system.

FIG. 8 is a diagram showing an output format in the initial stage of high-order data according to the conventional method.

FIG. 9 is a diagram showing a final output format of high-order data according to the conventional method.

FIG. 10 is a block diagram showing a specific configuration of a conventional multiplexing device.

FIG. 11 is a block diagram showing a specific configuration of a conventional demultiplexer.

FIG. 12 is a timing chart showing the phase relationship between high-order data and low-order clocks.

FIG. 13 is a diagram showing an output format of high-order data generated by a conventional multiplexing device.

[Explanation of symbols]

11-112 ... Low-order encoder, 1a, 1b ... A / D converter, 1c, 1d ... Multiplexer, 1e ... Low-order synchronous code generator, 1f ... Switching controller, 2 ... Multiplexing device, 2a ...
Higher-order clock generator, 2b ... 1/12 divider, 2c ... 1
/ 2048 divider, 2d ... P / S shift register, 3 ...
Modulator / transmitter, 4 ... Transmit antenna, 5 ... Receive antenna, 6 ... Receiver / demodulator, 7 ... Demultiplexer, 7a ... S
/ P shift register, 7b ... OR gate circuit, 7c ... 1
/ 12 frequency divider, 7d ... Higher-order synchronization code detector, 7e ... Frame synchronization pulse generator, 7f ... 1/12 frequency divider, 7g ...
S / P shift register, 81-812 ... Low-order decoder,
8a ... Decoder, 8b ... Low-order sync code detector, 8c ... Inversion gate circuit, 8d ... AND gate circuit, 8e ... 1/2
048 frequency divider, 8f ... 1/4 frequency divider, 8g ... D / A converter.

Claims (3)

[Claims] 1. A low-order encoder of N (N is a natural number) channel that generates low-order data of the same format having a synchronization signal from a transmitted digital signal, and a low-order encoder of these low-order encoders. A multiplexing device for sequentially multiplexing low-order data bit by bit to generate high-order data, and a transmission means for transmitting the high-order data generated by this device, and the receiving side are transmitted by the transmission means. A receiving means for receiving high-order data, a demultiplexing device for demultiplexing the high-order data obtained by this means into N-channel low-order data, and a demultiplexing device respectively provided for the N-channel low-order encoder, A digital signal multiplex communication system comprising an N-channel low-order decoder for inputting low-order data separated by the demultiplexer and reproducing a digital signal. The transmitting side selects any one of the N-channel low-order encoders to generate low-order data having a sync signal having a pattern different from those of other channels, and the sync signal having the different pattern. Is provided as a frame synchronization signal of the higher-order data, and the receiving side includes a synchronization signal detecting means for detecting the synchronization signals of the different patterns, and the multiplex based on the detection timing of this means. A digital signal multiplex communication system comprising: a channel adjusting means for adjusting a separation output channel of a separation device so as to match the channels of a low-order encoder and a low-order decoder. 2. The synchronization signal detection means is provided in a low-order decoder of the channel selected by the high-order synchronization signal generation means, and is used for frame synchronization of low-order data of the channel by detection of the synchronization signal and a detection signal. 2. The channel adjusting means sends the phase adjusting signal to the demultiplexing device until the detection signal is generated, thereby changing the channel phase of the demultiplexing device. Digital signal multiplex communication system. 3. The synchronization signal detecting means is provided in the demultiplexing device, detects the synchronizing signals of the different patterns at N-bit intervals to generate a detection signal, and the channel adjusting means comprises the demultiplexing device. 2. The digital signal multiplex communication system according to claim 1, wherein the high-order data is separated from the N-channel low-order data and output after the high-order data is frame-synchronized by the detection signal. ..