JPS57180244A - Multiplexing system - Google Patents

Multiplexing system

Info

Publication number
JPS57180244A
JPS57180244A JP6335881A JP6335881A JPS57180244A JP S57180244 A JPS57180244 A JP S57180244A JP 6335881 A JP6335881 A JP 6335881A JP 6335881 A JP6335881 A JP 6335881A JP S57180244 A JPS57180244 A JP S57180244A
Authority
JP
Japan
Prior art keywords
sets
multiplexing
time slot
time slots
bit rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6335881A
Other languages
Japanese (ja)
Inventor
Seiichiro Shigaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6335881A priority Critical patent/JPS57180244A/en
Publication of JPS57180244A publication Critical patent/JPS57180244A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To realize simplification, by inputting data from an external device in synchronizing with the output of a timing pulse generator, in a multiplexing system of an input digital signal having a relation of a constant integer ratio. CONSTITUTION:When a transmission line bit rate and an input signal bit rate are M:N, N sets of transmission data time slots in M sets of time slots are provided, and in N sets of the time slot, M/N and (M/N)+1 of mutual intervals are uniformly arranged, and a plurality of input signals h1 and h2 are inputted from the external device in response to the time slots, and the input signals h1 and h2 are arranged in the time slot a1 or the time slot a2 with different phase for multiplexing. Thus, multiplexing can be made with a simple device.
JP6335881A 1981-04-28 1981-04-28 Multiplexing system Pending JPS57180244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6335881A JPS57180244A (en) 1981-04-28 1981-04-28 Multiplexing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6335881A JPS57180244A (en) 1981-04-28 1981-04-28 Multiplexing system

Publications (1)

Publication Number Publication Date
JPS57180244A true JPS57180244A (en) 1982-11-06

Family

ID=13226943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6335881A Pending JPS57180244A (en) 1981-04-28 1981-04-28 Multiplexing system

Country Status (1)

Country Link
JP (1) JPS57180244A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341021B2 (en) * 1972-12-22 1978-10-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5341021B2 (en) * 1972-12-22 1978-10-31

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