JPS61294944A - Synchronizing multiplex conversion system - Google Patents

Abstract

PURPOSE:To improve the flexibility of multiplexing by providing a function inhibiting the output of the 5th speed conversion circuit when one of inputs from the 1st to the 4th speed conversion circuit is a 2.048Mb/s signal and multiplexing the output and a separation function of its inverse conversion so as to allow mixed allocation of a 1.544Mb/s signal and 2.048Mb/s signal. CONSTITUTION:In multiplexing the 2.048Mb/s signal, since 120 octet is exceeded by IN1-IN5, the IN1-IN4 are used. This is because the output of a NOR gate 6 goes to an L level and a selection circuit 8 selects always the output of an OR gate 5 and a maximum 120 octet is multiplexed while including even a case all IN1-IN4 are the 2.048Mb/s signals. On the other hand, a separation circuit uses a frame synchronizing circuit 9 for a 8.192Mb/s multiplexing signal to drive a gate pulse generating circuit 10, gates pulses 11-1-11-5 for the 1.544Mb/s signal and gate pulses 12-1-12-4 for 2.048Mb/s signal are used and the result is separated into OUT1-OUT5 by the inverse operation to the multiplexing by the speed conversion circuits 13-1-13-5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous multiplex conversion system for digital signals, and particularly to a TS44MVB signal having 24 channels and a TS44MVB signal having 24 channels.
A synchronous multiplex conversion method in which a 2,048 MVB signal having 2,048 channels is multiplexed into an 8,192M signal having 120 channels in octet units. The method is 1.
Synchronous multiplex conversion method of five 544 Mb/g signals and 8.192 M b/s signal, or 2.048 Mt)/8
It was a synchronous multiplex conversion system of four signals and an 8.192 Mb//I signal.

[Problem that the invention seeks to solve]

The conventional synchronous multiplex conversion method mentioned above is 1.544M
It is synchronous multiplex conversion of 5 b/s signals or 4 2.048 MJs signals and 8.192 Mb/a signals, and when 1.544 Mb/s signals and 2.048 Mjs signals coexist, It had the disadvantage of not being able to respond.

[Failure to solve the problem]

A synchronous multiplexing scheme according to the invention is a synchronous multiplexing scheme of a 1,544M11/] signal with 24 channels and a 2,048 Mb,4 signal with 3o channels and an a192Mb/s signal with 120 channels.

The above 1.544Mti in the first to fourth speed conversion circuits
signal or the above 2.04.8 M t1/s signal by gate pulse in octets 8.192
The speed of the 1.544M signal is converted into an 8.192MJs burst signal in a fifth speed conversion circuit, and at least one of the inputs to the first to fourth speed conversion circuits is converted into an Mb/I burst signal. One is 2.048 Mb/s
If it is a signal, this is a synchronous multiplex conversion system characterized by having a function of inhibiting the output of the fifth speed conversion circuit and multiplexing it, and a separation function that is the inverse conversion of the signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1 and 2 are diagrams showing the timing for explaining the structure and operation of an embodiment of the synchronous multiplex conversion system according to the present invention, respectively.

1.544 Mb/s (24 octets) or 2.
048M$ (30 octets) input signal IN1~INS
are respectively input to speed conversion circuits 1-1 to 1-5,
Both are burst output signals of a and 192 Mt%s. The phase of this burst output signal is determined by the gate pulse generation circuit 4 and is 1.544 Mb at the timing shown in FIG.
Gate pulses 2-1 to 2-5 and 2.0 for /s signal
Gate pulses 6-1 to 6-4 for 48 M b/s signals
will be synchronized. Speed conversion circuits 1-1 to 1-5 are usually 1
．． 544M or 2.048M7s signal because it is configured in an interface module that is an expansion unit.
Output terminal E of speed conversion circuits 1-1 to 1-5 is 1.544
+'L'' level for M11//I, 2.048M1
It is possible to set the operating oak to the "H" level.

When IN1 to INS are all 1.544MV'9 signals.

The signals from INI to IN4 are multiplexed by OR gate 5, while the signal from INS is such that the output of NOR gate 6 is at H level.9. Based on the selection control signal output from the AND gate 7, the selection circuit 8 multiplexes 120 octents.

Also at least one 2. When multiplexing o4sMt%s', IN1 to IN4 are used because IN1 to INS exceed 120 octets. This is N
The output of OR gate 6 becomes 6Ll level and 1 selection circuit 8
This is due to the fact that the output of the OR gate 5 is always selected.

With this, all 9 IN1 to IN4 are 2.048M1
1/! A maximum of 120 octets are multiplexed, including the case of 1 signal.

On the other hand, regarding the separation circuit, the gate pulse generation circuit 10 is driven by the frame synchronization circuit 9 of the 8.192 Mt)/s multiplexed signal, and the gate pulses 11-1 to 11-5.2 for the 1.544 Mb/s signal are generated. The gate pulses 12-1 to 12-4 for the .048 Mb/s signal cause the speed conversion circuits 13-1 to 13-5 to operate in the opposite manner to multiplexing.
It is separated into UT 1 to OUT 5. The timing diagram in Figure 2 shows the multiplexing and demultiplexing gate pulses (e.g. 3-1
and 12-1) are expressed in the same phase, but this is to simplify the description, and the relative phases of multiplexing and demultiplexing are generally arbitrary.

〔Effect of the invention〕

As is clear from the above explanation, according to the synchronous multiplex conversion method according to the present invention, 1.544Mk+/+ signal and 2
．． Since it is possible to accommodate a mixture of 0.048MJs signals, the flexibility of multiplexing can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the synchronous multiplex conversion system according to the present invention, and FIG. 2 is a timing chart of gate pulses of the device shown in FIG. 1. Explanation of symbols: ]-1 to 1-5 are speed conversion circuits. 2-1 to 2-5 are gate nodes for 1.544 M b/s signals. 3-1 to 3-4 are gate nodes for 2.048 M b/s signals.

Claims (1)

[Claims] (1) 1.544 Mb/s signal with 24 channels and 2.048 Mb/s signal with 30 channels and 1
In a synchronous multiplex conversion method with an 8.192 Mb/s signal having 20 channels, the first to fourth speed conversion circuits convert the 1.544 Mb/s signal or the 2.048 Mb/s signal
The speed of the Mb/s signal is converted into an 8.192 Mb/s burst signal using a gate pulse in units of octets, and the 1.544 Mb/s signal is converted into an 8.192 Mb/s burst signal by a fifth speed conversion circuit.
．． The speed is converted to a 192 Mb/s burst signal, and the first
at least one of the inputs to the fourth speed conversion circuit from 2
．． 048 Mb/s signal, the synchronous multiplex conversion system is characterized by having a function of inhibiting the output of the fifth speed conversion circuit and multiplexing it, and a separation function that is the inverse conversion thereof.