JPS6220438A - Parallel operation type frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To prevent the step-out of frame synchronization even if a selector circuit is operated, by connecting a phase compensating delay circuit between a circuit which expands a serial input in parallel and the selector circuit which selects the output and connects it to a frame synchronizing circuit. CONSTITUTION:The serial signal inputted to an input terminal 10 is expanded to the first-third signals 1-3 by a serial/parallel converting circuit (S/P CONV) and they are inputted to the first-third selector circuits (SEL1-3). Phase compensating delay circuits D1 and D2 are interposed between the circuit S/P CONV and the circuit SEL1, and outputs 2 and 3 are delayed and are inputted to the circuit SEL1. The circuit SEL1 selects one of outputs 1-3 and connects it to a frame synchronizing circuit SYNC, and the phase is not changed for switching among outputs 1-3 after frame synchronization is established once.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frame synchronization circuit of a digital multiplex converter that multiplexes and demultiplexes a plurality of digital signals, particularly when the multiplexed signal before separation is high speed. This invention relates to a parallel operation type frame synchronization circuit used.

[Conventional technology]

Frame synchronization is normally performed on multiplexed signals before separation, but as the speed of multiplexed signals increases, this becomes difficult and parallel operation is forced.

When using such a parallel-operating frame synchronization circuit, it is advantageous to make the frame structure of the multiplexed signal suitable for it. FIG. 2 is an example of a frame structure suitable for a parallel operation type frame synchronization circuit, and shows the case of three multiple currents. FIG. 2(a) is a multiplexed signal, and when it is serial/parallel converted, the three signals shown in FIG. 2(b) are obtained, and these three signals have exactly the same frame structure. In addition, in FIGS. 2(a) and (b), 1
is the position of the first channel, 2 is the position of the second channel,
3 indicates the position of the third channel, and F indicates the position of the frame pulse. A parallel operation type frame synchronization circuit for such a frame configuration can be realized, for example, by the circuit configuration shown in FIG.

The signal input to the input terminal (10) is input to the first serial/parallel conversion circuit (S/P C0NV). expanded into second and third signals (1, 2, 3); It is input to the second and third selector circuits (SELL, 2.3). 1st
The output of the selector circuit (SELI) is input to the frame synchronization circuit (SYNC), and frame synchronization is established only for the first signal (1) developed in parallel. Then, the second file expanded in parallel. The third signal (2, 3) is equivalent to when frame synchronization is automatically achieved. Here, the operation of the selector circuit (SELL, 2.3) is important.

In other words, serial/parallel conversion circuit (S/P C0NV)
There is no guarantee that the first channel in the multiplexed signal will be output as the first output (1) of the serial/parallel conversion circuit, and there are three possible states of the output of the serial/parallel conversion circuit as shown in FIG. Figure 4 (
Fig. 4(b) shows a state in which the first channel is output to the first output and the position of the frame pulse F of the three outputs is the same, and Fig. 4(b) shows a state in which the second channel is output to the first output. Figure 4 (C) shows a state where the third channel is output to the first output and the positions of the frame pulses F of the three outputs are different. It shows a different situation. Each selector circuit (S
ELL, 2.3) outputs the first channel to the first output terminal (11) and also outputs the first channel to the second output terminal (12) and the third output terminal (12).
The serial/parallel conversion circuit (S/P C0NV
) is used to select the output. Note that since the three outputs (1, 2, 3) of the serial/parallel conversion circuit have the same frame configuration, frame synchronization can be achieved regardless of the state of the selector circuit. In addition, the selector control circuit (
SEL C0NT) is a circuit that controls the selector circuit to correctly make the above selection.

[Problem that the invention seeks to solve]

However, the parallel operation type frame synchronization circuit shown in FIG. 3 has the following problems. The output of the serial/parallel conversion circuit is in one of the three states shown in Figure 4, which is usually known only when frame synchronization is established, so the selector circuit operates only after frame synchronization is established. It's going to happen. However, as is clear from Fig. 4, when the output states of the serial/parallel conversion circuit are as shown in Fig. 4(b) and (C), the positions, or phases, of the three output frame pulses F are different. Therefore, when the selector circuit is operated, the phase of the signal input to the frame synchronization circuit (SYNC) changes, resulting in a loss of frame synchronization.

Although it is not necessary to operate the selector circuit once frame synchronization is established again, it must be said that it is extremely disadvantageous that frame synchronization once established is lost.

[Means for solving problems]

The present invention has been made in order to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide a parallel operation type frame synchronization circuit that does not lose frame synchronization even when the selector circuit is operated.

The parallel operation type frame synchronization circuit of the present invention includes a serial/parallel conversion circuit that expands serial human power in parallel, a plurality of selector circuits that select the outputs thereof, and a frame synchronization circuit that is connected to one of the selector circuits. , is characterized by having a delay circuit inserted between a serial/parallel conversion circuit and a selector circuit.

Phase correction by the delay circuit makes it possible to prevent out-of-synchronization caused by operating the selector circuit, no matter what state the output of the serial/parallel conversion circuit is in.

〔Example〕

Next, the present invention will be explained in detail according to one embodiment thereof. FIG. 1 shows an example in which the present invention is applied to the circuit configuration shown in FIG. In Figure 1, the serial/parallel conversion circuit (S/P
A delay circuit (Di, 2) for phase correction inserted between the selector circuit (SELL, 2.3)
This is a newly added part in the present invention. The delay circuit (Dl) delays the output (2) of the serial/parallel conversion circuit to force the selector circuit (SELL), and the delay circuit (D2) delays the output (3) of the serial/parallel conversion circuit. and input it to the selector circuit (SEL2).

Now, assuming that the output of the serial/parallel conversion circuit (S/P C0NV) is in the state shown in Figure 4 (b), the first selector circuit (SELI) initially outputs the second channel. The first output (1) of the serial/parallel converter is selected, but once frame synchronization is established, the third output (3) of the serial/parallel converter outputs the first channel. It works like selecting. However, the connection was delayed! (D2> is included, so the selector circuit (S
Even if ELL, 2.3) is operated, the first selector circuit (
The position, that is, the phase, of the frame pulse F output from SELL does not change, and therefore frame synchronization does not occur. Further, when the output of the serial/parallel converter circuit is in the state shown in FIG. 4(C), the first selector circuit (SELL) initially 1 output (1) is selected, but once frame synchronization is established, the serial/
It operates to select the second output (2) of the parallel conversion circuit. However, since a delay circuit (Dl) is included in that connection, even if the selector circuit (SELI, 2.3> is operated), the position, that is, the phase, of the frame pulse F output from the first selector circuit [5EL1] will not change. It does not change and therefore frame synchronization is not lost.

Note that when the output state of the serial/parallel conversion circuit (S/P C0NV) is as shown in FIG. 4(a), the first channel is output to the first output (1), so the selector circuit There is no need for it to work. In this manner, in the parallel operation type frame synchronization circuit of FIG. 1, no matter what state the output of the serial/parallel conversion circuit is, frame synchronization does not occur due to the operation of the selector circuit.

Although the present invention has been described above for the case of a three-multiplex frame configuration, it is clear that the present invention can be applied regardless of the degree of multiplexing.

〔Effect of the invention〕

As described above, the parallel operation type frame synchronization circuit of the present invention has the advantage of operating without losing frame synchronization once established.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a frame configuration suitable for a parallel operation type frame synchronization circuit, and FIG. 3 is a diagram showing a conventional parallel operation type frame synchronization circuit for the frame configuration of FIG. 2. FIG. 4, which is a diagram showing an example of a circuit, is a diagram showing the state of the output of the serial/parallel conversion circuit of FIGS. 1 and 3. S/P C0NV... Serial/parallel conversion circuit 5ELL...... First selector circuit 5EL2......
・・Second selector circuit 5EL3 ・・・・・
......Third selector circuit 5YNC...
・・・・・・・・・・・・ Frame synchronization circuit SEL
C0NT... Selector control circuit Di, D2
・・・・・・・・・・・・ Delay circuit 10 ・・・
・・・・・・・・・・・・・・・・・・・・・ Input terminal 11 ・・・・・・・・・・・・・・・・・・・・・
...First output terminal 12 ...
...Second output terminal 13 ......
・・・・・・・・・・・・・・・ Third output terminal agent Patent attorney Yoshiyuki Iwasa－－－・－123123FFF + 23 1 2
3 -------(a) -------11F I + -
−−−−−−−−22F 2 2 −−
m-・----33F 33 ---
-(b) Figure 2 Figure 3---11F I + -
−−−−−−−−22F 2 2 −
...------ 3 3 F
3 3 -------(a) -------22F 2 2 -------1・-33F 3 3 ----------
-- 1 1 F +
1 -------(b) -------33F 3 3 ----
−−−−−− + l F
l + −−−−−1・・−2,
2F 2 2 -------(C) Figure 4

Claims (1)

[Claims] (1) A serial/parallel conversion circuit that expands serial input into parallel;
It is characterized by having a plurality of selector circuits for selecting the output, a frame synchronization circuit connected to one of the selector circuits, and a delay circuit inserted between the serial/parallel conversion circuit and the selector circuit. Parallel operation type frame synchronization circuit.