JPH0234053A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To constitute a circuit having a function for switching control of a bit phase delay similar to that of a conventional circuit with less number of components and to economize the design and manufacture of a device using the circuit by supplying a control signal for bit delay to a reset terminal of a D FF. CONSTITUTION:When a control signal given to a reset terminal R of the D FF 1 and controlling the bit delay is at an H level, the FF 1 is reset and its output Q goes to an L level. Then a digital signal input from the sender side is sent to the receiver side as a phase synchronizing circuit output via an AND gate 2 and an OR gate 3 as it is. Moreover, when the control signal is at an L level, the digital signal input goes to an L level, is delayed by one bit with the FF 1 and fed to the receiver side as a phase synchronizing circuit output through the gate 3. Thus, number of gate elements being the circuit components is decreased by 2 more than those of a conventional circuit but the entirely same control is applied to the input digital signal. Thus, the circuit having the switching control function for the bit phase delay equal to that of the conventional circuit is formed with less number of components and the design and manufacture of the device are economized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit phase synchronization circuit that controls whether or not to delay the bit phase of a digital signal by one bit in a digital transmission system.

[Prior Art] Conventionally, in normal digital transmission systems, serial-to-parallel conversion (S/P conversion) is performed to time-division multiplexed digital signals on the receiving side.
Depending on the means of /P conversion, a 1-bit phase shift may occur between the separated low-order group signals, and the circuit used to synchronize the phases in such a case is as follows.
There is something like the one shown in Figure 3. The operation of this circuit is explained in the fourth section.
This will be explained using digital signal waveforms of each part of the circuit shown in Figures (^) to (G). Note that the following explanation is expressed using positive logic.

The conventional circuit shown in FIG. 3 uses a combination of a D-type flip-flop 21, a NOT gate 22, AND gates 23 and 24, and an OR gate 25.

The operation of this circuit is based on the circuit configuration shown in Figure 3 and Figure 4 (^) ~
As can be seen from the signal waveforms of each part of the circuit in (G), if the control signal is "H" (lligh), the output from the D-type flip-flop 21 is changed to "L" (Low) by the AND gate 23.
), and the digital signal input from the transmitting side passes through the AND gate 24 and the OR gate 25 as is.
It is sent to the receiving side as a phase locked circuit output.

On the other hand, if the control signal is "L", the digital signal input from the transmitting side via the AND gate 24 becomes "L", and the digital signal input from the transmitting side is delayed by one bit by the D-type flip-flop 21. , and is sent from the AND gate 23 through the OR gate 25 to the receiving side as a phase locked circuit output.

[Problems to be Solved by the Invention] The conventional circuit shown in FIG. 3 described above is a so-called unit circuit for synchronizing a 1-bit phase shift in an S/P converter for time division separation. As multiplexing in digital transmission systems progresses, S/P conversion devices for time division separation also become more complex, and such unit circuits will be used in increasing quantities.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to configure a circuit having a bit phase delay switching control function equivalent to that of the conventional example with a smaller number of circuit elements, thereby making the design and manufacturing of time division separation devices more economical. The object of the present invention is to provide a phase-locked circuit that is advantageous.

In a phase-locked circuit configured to control switching of the output of the phase-locked circuit, an input is supplied to the data input terminal of a D-type flip-flop and the first input terminal of an AND gate, and the output of the D-type flip-flop is The AND output from the AND gate is taken out as a phase locked circuit output via an OR gate, and a control signal is supplied to the reset input terminal of the D-type flip-flop and the second input terminal of the AND gate, and according to the control signal, The present invention is characterized in that a signal having the same bit phase as the input or a signal whose phase is delayed by one bit from the input is taken out as the output of the phase locked circuit.

[Means for Solving the Problems] In order to achieve such an object, the present invention has a D-type flip-flop, and the input to the D-type flip-flop is controlled according to a control signal that controls the bit phase. According to the present invention, the output of a D-type flip-flop can be taken out directly as a phase-locked circuit output, or output from a D-type flip-flop. By using the reset function according to the signal input to the reset terminal, it is possible to reduce the number of logic elements to be combined with the D-type flip-flop, and this makes it possible to time-divisionally divide multiplexed digital signals. This makes it possible to more easily construct an effective S/P conversion device.

[Example] The present invention will be described in detail below with reference to the drawings.

An embodiment of the present invention is shown in FIG. 1, and examples of digital signal waveforms at various parts thereof are shown in FIGS. 2(^) to (F).

In FIG. 1, 1 is a D-type flip-flop used to delay the digital signal input from the transmitting side by 1 bit, 2 receives the digital signal input and the control signal,
an AND gate 3 that performs control to select, depending on the control signal, whether the digital signal input is taken out directly as a phase-locked circuit output, or when it is taken out as a phase-locked circuit output via a D-type flip-flop 1;
is an OR gate that obtains the OR output of the output Q of the D-type flip-flop 1 and the AND output of the AND gate 2,
The OR output is taken as the phase locked circuit output. As can be seen from the circuit configuration in Figure 1 and the digital signal waveforms of each part of the circuit in Figures 2 (A) to (F), the operation of this circuit is such that when the control signal is 'H', the D-type flip-flop is activated. 1 is reset, its output Q becomes L'', and the digital signal input from the transmitting side passes through the AND gate 2 and the OR gate 3 as it is, and is sent to the receiving side as a phase synchronized circuit output.

On the other hand, if the control signal is "L", the digital signal input from the transmitting side via the AND gate 2 becomes "L", and the digital signal input is delayed by one bit by the p-type flip-flop 2 and then sent to the OR gate 3. The signal is sent to the receiving side as a phase-locked circuit output.

In other words, between the circuit of this embodiment and the circuit of the conventional example, the number of gate elements constituting the circuit of this embodiment is two compared to the conventional example (only two not gates 22 and AND gates 23). Despite the decrease, both can perform exactly the same control over input digital signals.

[Effects of the Invention] As is clear from the above, according to the present invention, a control signal for controlling a bit delay is supplied to a reset terminal that is not used in a D-type flip-flop of a conventional digital signal phase synchronization circuit. As a result, the number of gate elements used in combination with the D-type flip-flop of such a phase-locked circuit can be reduced. Therefore, according to the present invention, when configuring an S/P conversion device for time-division separation of multiplexed digital signals using a large number of phase-locked circuits, the configuration can be simplified. .

Therefore, the present invention is applicable not only to S/P converters but also to S/P converters of digital signals in general digital computers.
It is useful not only in conversion, but also as a 1-bit delay device in various applications.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part for explaining the circuit operation of FIG. 1, FIG. 3 is a block diagram showing an example of a conventional phase synchronization circuit, FIG. 4 is a waveform diagram of signals of various parts for explaining the circuit operation of FIG. 3. 1...D type flip-flop, 2...AND gate, 3...OR gate, 21...D type flip-flop, 22...not gate, 23.24...and gate, 25...・Orgate.

Claims (1)

[Claims] 1) A D-type flip-flop is provided, and the input to the D-type flip-flop is directly taken out as a phase synchronized circuit output, or the D-type flip-flop is In the phase-locked circuit, the input is supplied to the data input terminal of the D-type flip-flop and the first input terminal of the AND gate, Said D
The output of the D-type flip-flop and the AND output from the AND gate are taken out as the phase-locked circuit output through an OR gate, and the control signal is supplied to the reset input terminal of the D-type flip-flop and the second input terminal of the AND gate. and a signal having the same bit phase as the input or a signal whose phase is delayed by one bit from the input is extracted as the output of the phase synchronized circuit according to the control signal. synchronous circuit.