JPS62269432A - Parallel operation type frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To demultiplex a multiplex signal accurately by detecting to which channel of multiplex signals an output signal of a synchronizing circuit corresponds respectively and giving a selection signal to a selector circuit by a control circuit. CONSTITUTION:The titled circuit consists of a serial/parallel conversion circuit 20 outputting the 1st-nth conversion signals 21-23, frame synchronizing circuits 31-33 taking frame synchronization independently, selector circuits 51-53 selecting one of signals at each input terminal and giving an output, delay circuits 42, 43 retarding the signal at the input terminal by one bit of the conver sion signal, and a control circuit 60 detecting to which channel of multiplex signals an output signal corresponds and giving the result to the selector circuits 51-53. In the stage where the frame synchronization is taken, what order chan nel in the multiplex signals the output of the frame synchronizing circuit corresponds is recognized. In rearranging the outputs of the circuits 31-33 by the selector circuits 51-53, accurate demultiplexing is applied.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a frame synchronization circuit for a digital multiplex converter that multiplexes and demultiplexes a plurality of digital signals, particularly when the multiplexed signal before one division is high speed. The present invention relates to a parallel operation type frame synchronization circuit used in

[Conventional technology]

Frame synchronization is normally performed by one frame synchronization circuit for multiplexed signals before separation, but as the speed of multiplexed signals increases, frame synchronization by one frame synchronization circuit becomes difficult. A synchronous circuit must be used. When using a parallel-operating frame synchronization circuit, it is advantageous to have a frame structure of the multiplexed signal suitable for it. Figure 2 is.

This is an example of a frame structure suitable for a parallel operation type frame synchronization circuit, and shows a three-multiplex case.

FIG. 2(a) shows the multiplexed signal 10, and when it is serial/parallel converted, three signals (first to third converted signals) are obtained as shown in FIG. 2(b). 2], 22, 23 However, these five signals have exactly the same frame structure. A parallel operation type frame synchronization circuit for this frame configuration can be realized by the circuit configuration shown in FIG. 3, for example.

The multiplexed signal 10 input to the input terminal is expanded into five signals (first to sixth converted signals) 21, 22, and 23 by a serial/parallel conversion circuit (s, "pCONV) 20, and or the sixth frame synchronization circuit (5YNC1,
5YNC2°5YNC3) Frame synchronization is performed independently at 31, 32, and 33.

[Problems to be Solved by the Invention] However, the parallel operation type frame synchronization circuit shown in FIG. 5 has the following problems. Namely.

There is no guarantee that the first channel in the multiplexed signal will be input to the first frame synchronization circuit 31.

The first to fifth converted signals 21, 22, and 23 obtained as the outputs of the serial/parallel converter circuit 20 can have six types shown in FIG. 4 depending on the initial state of the serial/parallel converter circuit. Therefore, even if frame synchronization is achieved, accurate separation cannot be performed. Moreover, as shown in Figure 4, the phases differ in the three states, and the frame synchronization pulse F
There is a time difference between the positions of This causes the complexity of the circuits subsequent to the frame synchronization circuit.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a parallel-operating frame synchronization circuit that can accurately separate multiplexed signals.

Remaining days below [Means for solving problems] According to the invention.

Multiplexed signal (to) with a multiplicity of n (n is an integer of 2 or more)
i received, expanded in parallel, and the first to nth converted signals (21
~23) A full output serial/parallel conversion circuit (20).

The first to nth frame synchronization circuits (31 to 3) receive the first to nth conversion signals and perform frame synchronization independently.
3).

each has a first to nth input terminal connected to an output terminal of the first to nth frame synchronization circuit, and according to a first to nth selection signal, each of the first to nth first to nth selector circuits (51 to 53) that select and output one of the signals at the input terminal of the circuit;

inserted between the output ends of the frame synchronization circuits other than the first frame synchronization circuit among the first to n-th frame synchronization circuits and the input ends of the first to n-th selector circuits, a delay circuit (42, 43) that delays the entire signal at the input end by one bit of the converted signal;

Said 1st. - Control to detect which channel in the multiplexed signal each output signal of the n-th frame synchronization circuit corresponds to, and to apply the first to n-th selection signals to the first to n-th selection circuits. A parallel operation type frame synchronization circuit is obtained which is characterized by having the circuit (60).

At the stage when frame synchronization is achieved, it is known which channel in the multiplexed signal the output of a certain frame synchronization circuit is. Therefore, accurate separation can be achieved by rearranging the outputs of the frame synchronization circuit using a selector circuit. moreover,
If a delay circuit is inserted into an appropriate signal between the frame synchronization circuit and the selector circuit, the phases of the output signals of the selector circuit will be aligned.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example in which the present invention is applied to the circuit configuration shown in FIG. In FIG. 1, a delay circuit (D) after the second and third frame synchronization circuits (32, 33) 42.
43. First to sixth selector circuits (5ELL,
5EL2.5EL3)51.52.53.

and a control circuit (CONT) 60 are newly added parts in the present invention. The delay circuits 42 and 43 receive the output signals of the second and sixth frame synchronization circuits 32 and 33,
The converted signal 22 and B are delayed by one bit. The control circuit 60 includes the first to sixth frame synchronization circuits 31 to 3.
It is detected which channel in the multiplexed signal 10 each of the three output signals corresponds to, and the first to fifth selection signals are applied to the first to third selector circuits 51 , 52 , 53 . First to third selector circuits 51, 52
, 53, the signal output from the first frame synchronization circuit 31 and the delay circuit 4.2 according to the first to sixth selection signals.
, 4.3 is selected and output.

The state of the output of the first serial/parallel conversion circuit 20 is now shown in Figure 4 (b
), the first selector circuit 51 .
Second selector circuit 52. The third selector circuit 53 is
a third frame synchronization circuit 33 . First frame synchronization circuit 31. It operates according to the first to sixth selection signals to select the output of the second frame synchronization circuit 32, and accurately separates the first channel, second channel, and sixth channel in the multiplexed signal. do. 1, the signals from the frame synchronization circuits 32 and 33 to the selector circuits 51 and 52 are transmitted through delay circuits 42 and 431 . (The phase of the output signal of the selector circuit is the same.) The state of the output of the serial/parallel converter circuit is as shown in Fig. 4(a) (or as shown in Fig. 4(c)).
), if the condition is 1. Second. The sixth selector circuits 51, 52, 53 are the first selector circuits 51, 52, 53. Second. By selecting all the outputs of the fifth frame synchronization circuit (second, third, and first frame synchronization circuits), the outputs of the first to fifth selector circuits 51152 and 53 respectively become multiplexed signals. The 1st channel, 2nd channel, and 6th channel.

The phase of the trench is also the same. Although only the case of 6-multiplexing has been described here, it is obvious that the invention can also be applied to cases where the multiplicity is different.

〔Effect of the invention〕

As described above, according to the two parallel-operating frame synchronization circuits of the present invention, it is possible to accurately separate multiplexed signals, and since the phases of the output signals are the same, subsequent circuits are simplified. So.

Very useful.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a frame configuration suitable for a parallel operation type frame synchronization circuit, and FIG. 3 is a diagram showing a conventional parallel operation type frame synchronization circuit for the frame configuration of FIG. 2. A diagram showing an example of the circuit, and FIG.
FIG. 7 is a diagram showing the state of the output of the serial/parallel conversion circuit shown in FIGS. In FIGS. 1 and 6, 20 is a serial/parallel conversion circuit;
3], , 32.33 is the first. Second. 6th frame synchronization circuit, 42.43 is a delay circuit, 51, 52.5
3 is the first, second . The fifth selector circuit 60 is a control circuit. In FIGS. 2 and 4, F is the position of the frame pulse, and 1, 2.3 are the 11th, 2nd, . . . , respectively. This is the position of the sixth channel. (Q) 10 123123FFF123123
---Figure 3

Claims (1)

[Claims] 1. A serial/parallel conversion circuit that receives a multiplexed signal with a multiplicity of n (n is an integer of 2 or more), expands it in parallel, and outputs first to nth converted signals; first to nth frame synchronization circuits that receive first to nth conversion signals and perform frame synchronization independently; and first to nth frame synchronization circuits each connected to an output end of the first to nth frame synchronization circuits first to nth selector circuits having input terminals and selecting and outputting one of the signals of each of the first to nth input terminals according to the first to nth selection signals; and inserted between the output ends of the frame synchronization circuits other than the first frame synchronization circuit among the first to nth frame synchronization circuits and the input ends of the first to nth selector circuits. a delay circuit that delays the signal at the input end by one bit of the converted signal, and detects how many channels in the multiplexed signal each output signal of the first to n-th frame synchronization circuits corresponds to. and a control circuit for applying the first to nth selection signals to the first to nth selection circuits.