JPS63262938A - Fast synchronization circuit - Google Patents

Abstract

PURPOSE:To secure a system which takes out output data in a form of parallel signal and aligns the phase of the parallel signal to be outputted, that is, TSSI (Time Slot Sequence Integrity), by delaying an inputted serial digital signal by a prescribed number of bits by a variable length shift register provided at the front step of a serial-parallel conversion circuit. CONSTITUTION:A frame synchronization pattern is detected from either plural frame synchronization pattern detection circuits (300-1-300-n) provided in parallel, and the position of the pattern at parallel arrangement is detected by a synchronizing position detecting means 600. Corresponding to the above, a control signal which delays an input signal so as to set a frame synchronizing signal at the beginning of the parallel arrangement is added on a signal delay means 500, and the signal delay means 500 delays the input signal by the number of bits decided by the control signal. In such a way, the frame synchronizing signal is set at the forefront of the parallel output of the serial-parallel conversion circuit 200, and no mixing of the data of a preceding and a succeeding frames can be prevented from occurring, and also, the TSSI can be secured.

Description

[Detailed description of the invention] [1 already required] In a high-speed synchronization circuit that converts a serial digital signal into a parallel signal and detects a frame synchronization pattern, the position of the frame synchronization signal is detected from the parallel outputs of the frame synchronization pattern detection circuit. and by the control signal determined by it,
By delaying the input serial digital signal by a predetermined bit using a variable length shift register provided before the serial-to-parallel conversion circuit, the output data is extracted in the form of a parallel signal, and the phase of the output parallel signal is adjusted. TSSI(T
ime 5lot 5equence Integri
ty).

[Industrial application field]

The present invention relates to improvements in high-speed synchronization circuits for digital signals.

In digital transmission, synchronization signals are required for sending, receiving, or branching signals. As the amount of transmitted information increases, multiplexing progresses, and signal speeds become faster, signal processing becomes difficult.
It is desirable that the circuit ensure SI.

[Conventional technology]

FIG. 5 is a block diagram showing the configuration of a conventional high-speed synchronous circuit.

FIG. 6 is an input/output signal arrangement diagram of an example of a serial-to-parallel conversion circuit.

Input data A, for example, 3 pins - (AI, A2, A3)
, and the frame synchronization pulse F is defined as Fl, F2, F
3. Assuming that it consists of a combination of F4, the input serial digital signal is arranged as shown in Figure 6(a), and a frame synchronization pulse F is inserted in the first bit of each frame consisting of 4 bits. . This frame synchronization pulse is inserted in a predetermined number of consecutive frames so as to have a regular level pattern, eg, a "1011" shape.

This level pattern is an example where the number of repeated frames is four. Only the frame signals F of four consecutive frames are taken out one after another, and if the above-mentioned regular pattern is detected, a frame synchronization signal is obtained.

In FIG. 5, a serial digital signal from a transmission line 1 is input to a shift register 21 of a serial/parallel conversion circuit 2. In FIG.

The shift register 21 has, for example, 4 bits, which corresponds to the number of bits included in each frame, and converts the serial signal into 4-bit parallel signals P1 to P4. When a signal as shown in FIG. 6(a) is input to the shift register 21, the four parallel output parts P1 of the shift register 21
.about.P4 outputs a Pi-F4 signal delayed by 1 bit each as shown in FIG. 6(b) at a certain point in time.

Now, if we take a point in time when the A2 bit signal is output from the Pi terminal of the shift register 21, P2 to P4 are shown in Figure 6 (
The bits that match in the vertical direction of b), that is, the signal of the A3 bit one bit before for F2, the signal of the F1 bit for F3,
Further, a signal of the A1 bit is outputted to P4.

Register 22 contains the next A2 bit and the following A3 bit.
, F2, and A1 bits are input to the shift register 21, the previous parallel output signals of P1 to P4 are held at ports 1 to 4, and are supplied to frame synchronization pattern detection circuits 3-1 to 3-4.

When the next new 4-bit signals, namely A2, A3, F3, and AI bits, are input to the shift register 21, F4
An A1 bit signal from the terminal, an F2 bit signal from the F3 terminal, an A3 bit signal from the F2 terminal, and an A2 bit signal from the Pi terminal are supplied to the register 22 and held there.

In this way, A2 is output from the output Q1 of the register 22.
A bit signal is output from Q2, an A3 pinto signal is output, an F2 bit signal is output from Q3, and an A1 bit signal is output from Q4.

Since the signals supplied from the old to Q4 output terminals of the register 22 to the frame synchronization pattern detection circuits 3-1 to 3-4 are given only one bit for every four bits of the input signal, the signal speed is 1/1. Reduced to 4. Therefore, the complaint synchronization pattern detection circuits 3-1 to 3-4 are
It is sufficient to operate at 1/4 the signal speed of the serial digital signal.

Each parallel output section of the serial-to-parallel conversion circuit 2 is provided with frame synchronization pattern detection circuits 3-1 to 3-4 having the same configuration. Each frame synchronization pattern detection circuit 3-1 to 3-4 is
Including a circuit that directly outputs the input from the register 22 to the synchronization pattern identification circuits 32-1 to 32-4, there are (number of frames of frame synchronization pattern repetition - 1) shift registers 31-11 to 31-13, . 31-41~3
The output parts of 1-43 are connected to the synchronization pattern identification circuit 32, respectively.
-1 to 32-4.

FIG. 5 shows a case where the frame synchronization pattern is repeated in four frames, and each shift register has one bit.

Synchronous pattern identification circuits 32-1 to 32-4 are NAND circuits 34-1 to 34-4 and inverters 33-1 to 33-4.
It consists of a register 22 and a shift register 31-1.
1-31-13, ~. When an output of 1011" is given from any one set of 31-41 to 31-43, the inverter changes "0" to "1" so that all the inputs of the NAND circuit become "1", and the NAND A "0" pulse is output from the circuit to identify the frame synchronization pulse.

In this way, the frame synchronization pattern detection circuit 3-1~
When a frame synchronization pattern is detected in any one of 3-4, an "O" pulse is output from the NAND circuit.

This 0'' output is applied to the input of switch contact 4, turning on the switch contact that had been turned off.Then, the serial digital signal input from transmission line 1 to serial-parallel conversion circuit 2 is branched. The input signal that was taken out and applied to the input a of the contact 4 of the switch is taken out as output data at the time when a frame synchronization pattern is detected.

[Problem that the invention seeks to solve]

However, in the conventional high-speed synchronous circuit described above,
Frame synchronization pulses can be detected from serial digital signals using a serial-to-parallel conversion circuit, but since the data is extracted from the serial signal as a signal following the detected frame synchronization pulses, the higher the speed of the serial digital signals, the more accurate the data becomes. There was a problem that it became difficult to obtain output data.

[Means for solving problems]

The above problem is caused by the serial/parallel conversion circuit 2 that converts a serial digital signal into a parallel signal by n bits, as shown in Figure 1.
00 and frame synchronization pattern detection circuits 300-1 to 300-n connected to each parallel signal output section, the position of the frame synchronization signal is detected from the output signal of the frame synchronization pattern detection circuit. The present invention has a synchronization position detection means 600 that outputs a corresponding control signal, and a signal delay means 500 connected to the front stage of the serial/parallel conversion circuit 200 and delaying the input serial digital signal by a predetermined bit determined by the control signal. The solution is provided by the inventive high speed synchronous circuit.

[Effect]

In FIG. 1, a plurality of frame synchronization pattern detection circuits 300-1 to 300-n arranged in parallel detect a frame synchronization pattern from any one of them, and a synchronization position detection means 600 detects the frame synchronization pattern in the parallel arrangement. Detect location. Correspondingly, a control signal is applied to the signal delay means 500 to delay the input signal so that the frame synchronization signal comes first in parallel.

The signal delay means 500 delays the input signal by the number of bits determined by the control signal.

As a result, the frame synchronization signal comes at the beginning of the parallel output of the serial/parallel conversion circuit, and the data of the previous and subsequent frames are not mixed, and TSS r is ensured.

Furthermore, since the serial data is converted into parallel data by the serial/parallel conversion circuit to reduce the speed, it is possible to sufficiently follow and process even high-speed input serial signals.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a high-speed synchronous circuit according to an embodiment of the present invention.

FIG. 3 is a diagram of a synchronization position detection circuit used in the embodiment.

Figure 1 is a circuit diagram of a variable length shift register used in the embodiment.

The same reference numerals indicate the same objects throughout the figures.

In Fig. 2, the variable length shift register 5 consists of 2 x (number of bits in one frame) - 1, and in this case, as shown in Fig. 6(a), one frame consists of 4 bits. Then, the variable length shift register 5 consists of 7 bits. The human-powered serial digital signals are temporarily held here. Thereafter, the signal is converted into a parallel signal via the serial/parallel conversion circuit 2 and the frame synchronization pattern detection circuits 3-1 to 3-
Added to 4.

The outputs of the frame synchronization pattern detection circuits 3-1 to 3-4 are applied to a synchronization position detection circuit 6 comprising a fixed storage device (hereinafter referred to as ROM). Frame synchronization pattern detection circuit 3
A frame synchronization pulse is detected in any one of -1 to 3-4 and outputs "0", and the other outputs are "1", so
When these are input to the synchronization position detection circuit 6, one of them is "O" and the other three are "1", resulting in a combination of inputs. As shown in FIG.
It is used as an address as is in the ROM.

When the output of the frame synchronization pattern detection circuit 3-1 is a frame bit, the address of the ROM is "01".
11", and outputs a control signal that is delayed by θ bits (that is, not delayed at all). Also, when the output of the frame synchronization pattern detection circuit 3-2 is a frame bit, the ROM address is "1011". Yes, TSS
In order to secure I, a control signal for delaying the input signal to the variable length shift register 5 by 3 bits is output and input to the variable length shift register 5. Similarly, when the output of the frame synchronization pattern detection circuit 3-3 is a frame bit, a control signal is inputted into the variable length shift register 5 to delay it by 2 bits, and to delay it by 1 bit when it is 3-4.

As shown in FIG. 4, the variable length shift register 5 includes a switch contact 12, 14, 16, 1 bit delay shift register 13, and a 2-bit delay shift register 13, which is turned on/off by the above-mentioned control signal and is made up of, for example, a relay. It consists of a circuit in which delay shift registers 15 are connected in series. For example, when delaying by 1 bit, connect contact 12 of switch 7 to d so that the input serial signal passes through 1-bit delay shift register 13, and connect contact 14 of the switch to f to perform 2-bit delay shift. Register 15 is bypassed.

As a result, the input serial signal is delayed by the control signal according to the frame focus position, and the parallel output signal of the serial-to-parallel conversion circuit 2 reaches the right end (Q4) of the frame synchronization signal, as shown in Figure 2. output one frame of data.

In this way, the TSSI of the output parallel signals is ensured.

Also, the output data is 01, Q2, Q3 of the serial/parallel converter circuit 2.
A1, A2,
Analog output data that is continuous with A3 can be obtained.

In the embodiment of the present invention, one type of data consisting of three bits has been described, but the present invention is not limited to the type of data or the number of bits, and can be applied to a plurality of data.

〔Effect of the invention〕

As described above, according to the present invention, high-speed signal processing becomes possible by converting input serial data into parallel data to reduce the speed.

Furthermore, by matching the phases of the parallel data output from the high-speed synchronous circuit, it is possible to ensure TSSI.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing the configuration of a high-speed synchronization circuit according to an embodiment of the present invention, Fig. 3 is a synchronization position detection circuit diagram used in the embodiment, and Fig. 4 is FIG. 5 is a block diagram showing the configuration of a conventional high-speed synchronous circuit; FIG. 6 is an input/output signal arrangement diagram of an example of a serial-to-parallel conversion circuit. In the figure, 200 is a serial/parallel conversion circuit, 300 is a frame synchronization pattern detection circuit, 500 is a signal delay means, and 600 is a synchronization position detection means.

Claims (1)

[Claims] A serial/parallel conversion circuit (200) that converts a serial digital signal into a parallel signal by n bits, and a frame synchronization pattern detection circuit (300-1) connected to each parallel signal output section.
~300-n), a high-speed synchronization circuit comprising: synchronization position detection means (600) for detecting the position of the frame synchronization signal from the output signal of the frame synchronization pattern detection circuit and outputting a corresponding control signal; Serial-to-parallel conversion circuit (
A high-speed synchronous circuit characterized in that it has a signal delay means (500) connected to the front stage of the circuit (200) for delaying an input serial digital signal by a predetermined bit determined by the control signal.