JPH04252628A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain a small-scale frame synchronizing circuit which performs the high-speed operation by connecting a synchronizing pattern detecting circuit consisting of a shift register to an arbitrary output of a serial-parallel conversion circuit and inputting the detection result to a synchronism position detecting circuit and controlling a delay circuit connected to the preceding stage of the conversion circuit to change the extent of delay. CONSTITUTION:A synchronizing pattern detecting circuit 3 consisting of a shift register is connected to arbitrary output of a serial-parallel conversion circuit 1, and the detection result is inputted to a synchronism position detecting circuit 4, and a delay circuit 6 connected to the preceding stage of the circuit 1 is controlled. The high-speed digital signal inputted to the frame synchronizing circuit is separated into four systems by the circuit 1 in this manner, and pattern collation is performed with respect to an arbitrary sequence by the circuit 3. Since it is probable that the output of the circuit 1 is cyclically switched by four systems of collation patterns in accordance with the initial state of a frequency dividing counter 2, a control pulse is given to the circuit to adjust the extent of delay of input data for each bit.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a frame synchronization circuit in digital transmission, and particularly to a frame synchronization circuit in digital transmission.
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This invention relates to means for constructing a high-speed synchronous circuit on a small scale while ensuring the following.

0002

[Prior Art] Conventionally, in a frame synchronization circuit for high-speed digital signals, in order to minimize the number of high-speed operating parts, the circuit shown in FIG.
It was structured like this. The high-speed digital signal on the digital transmission path is serially-parallel converted into a 1/N speed digital signal at the input of the frame synchronization circuit in order to reduce the speed of signal processing in subsequent stages. In FIG. 2, as an example, serial-to-parallel conversion is performed at a ratio of 1:4 (N=4), but this is not the case in the case of division. In order to detect the frame synchronization pattern of the digital signals that have been slowed down in parallel, pattern matching is performed for a specific channel by a synchronization pattern detection circuit 3 consisting of a shift register. Now, when a frame matching pattern is input as an input signal, depending on the initial state of the frequency division counter 2, there is a possibility that the parallel output of the serial/parallel conversion circuit 1 is switched to cycling by a number corresponding to the number of divisions. The channel selector 5 is controlled depending on which pattern is matched, and the order of output data is changed in accordance with the order of the input patterns. On the other hand, the frame information detected by the synchronization pattern detection circuit 3 is outputted as a frame synchronization pulse by the synchronization position detection circuit 4.

0003

[Problems to be Solved by the Invention] The conventional frame synchronization circuit described above performs synchronization pattern detection after serial-to-parallel conversion, but since the order of output data is changed depending on the initial state of the frequency division counter, the synchronization pattern sequence A channel selector is required to switch the order of the output data series according to the output data, and the circuit has the drawback of becoming large-scale.

0004

[Means for Solving the Problems] The frame synchronization circuit of the present invention connects a synchronization pattern detection circuit to the output of a serial-to-parallel conversion circuit controlled by a frequency division counter, and connects a synchronization pattern detection circuit to the output of a serial-to-parallel conversion circuit controlled by a frequency division counter. It has a configuration that controls a delay circuit connected upstream of the conversion circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows an embodiment of the present invention. A synchronization pattern detection circuit 3 consisting of a shift register is connected to any output of the serial-to-parallel conversion circuit 1, and the detection result is sent to the synchronization position detection circuit 4.
The delay circuit 6 connected to the front stage of the serial-to-parallel conversion circuit 1 is controlled. A high-speed digital signal input to the frame synchronization circuit is separated into four series by the serial/parallel conversion circuit 1. A synchronization pattern detection circuit 3 performs pattern matching for an arbitrary series. At this time, depending on the initial state of the frequency division counter 2, four matching patterns may be encountered, and the output of the serial/parallel conversion circuit 1 may be cyclically switched. Now, in the frame synchronization circuit (...F6F62828...)h=(
. . 1111011000101000 . . . ) when a repetitive digital signal is inputted will be described. At this time, the output of the serial-to-parallel conversion circuit 1 exists in states (1) to (4) as shown in FIG. In each case, the synchronization pattern detection circuit 3 performs pattern matching, and depending on which of the patterns (1) to (4) is matched, control is applied to the delay circuit connected to the preceding stage of the serial/parallel conversion circuit. By applying a pulse, the delay amount of the input DATA is adjusted bit by bit, and the 1st bit of the frame matching pattern is changed from the output signal 1 to 2 of the frame synchronization circuit.
The 1st bit can be extracted from the output signal 2, the 3rd bit from the output signal 3, and the 4th bit from the output signal 4.

[0006]

As explained above, the present invention connects a synchronous pattern detection circuit to the output of a serial-to-parallel conversion circuit controlled by a frequency division counter, and uses a synchronous position detection circuit to detect
The frame synchronization circuit, which is configured to establish bit synchronization and select the channel of the output data signal, controls the delay circuit connected to the front stage of the serial-to-parallel conversion circuit according to the series of synchronization matching patterns to change the amount of delay. By letting
This has the effect of realizing an extremely small-scale and high-speed frame synchronization circuit.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the present invention.

FIG. 2 is a conventional technique of the present invention.

FIG. 3 is the operating principle of the present invention.

[Explanation of symbols] 1 Serial to parallel conversion circuit 2 Divide counter 3. Synchronous pattern detection circuit 4 Synchronous position detection circuit 5 Channel selector 6 Delay circuit

Claims (3)

[Claims] Claim 1: A device for transmitting a digital signal having a frame synchronization pattern, in which a high-speed digital signal is input to a serial-to-parallel conversion circuit synchronized with a frequency division counter, and a synchronization pattern detection circuit is connected to the parallel output of the serial-to-parallel conversion circuit. 1. A frame synchronization circuit, characterized in that a synchronization position detection circuit controls the amount of delay of a delay circuit connected upstream of the serial-to-parallel conversion circuit, based on the results of connection and pattern matching. 2. The frame synchronization circuit according to claim 1, wherein the synchronization pattern circuit includes a shift register. 3. The frame synchronization circuit according to claim 1, wherein the synchronization position detection circuit controls the amount of delay of the delay circuit according to the series of pattern matching.