JPS63197210A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To form a clock switching part with a low-speed process switching circuit by providing a dividing circuit and a multiplying circuit before and after the clock switching part respectively. CONSTITUTION:An input clock is usually selected within a clock switching part 2 and supplied to a data processing part 1 to be synchronous with the input data. When this information produces a no-input state or a frame step-out state, a switch control part signal is sent to a clock processing part 2 from the part 1 and a clock is selected out of a local oscillation part 4. This switching action forms a frame within an intermediate repeating installation and delivers data. Then an input clock dividing circuit 5 and a multiplying circuit 3b having the same value as the dividing ratio of the circuit 5 are added to a clock switching circuit at the front and back sides of the part 2 respectively. As a result, the switching actions of high frequency clocks can be minimized and a clock switching action is carried out through a low-speed processing action.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an intermediate relay device for a backbone transmission line system. In particular, the present invention relates to a clock switching circuit for an intermediate relay device having a local oscillator.

〔overview〕

The present invention provides a clock switching means for switching between two clock signals having different frequencies, in which the frequency of one clock signal is divided and the frequency of the other clock signal is multiplied by an integer fraction of the frequency of the other clock signal. By multiplying the frequency of one clock signal after switching, clock switching can be performed at low speed.

[Conventional technology]

As shown in FIG. 2, a conventional intermediate relay device having a local oscillator is composed of a data processing section 1, a clock switching section 2, a clock multiplier circuit 3C, and a local oscillation section 4.
Data processing unit 1 constantly monitors data and clock,
If this information causes an unattended state or frame synchronization to occur, this input data is not determined to be correct information and is not output as data. At this time, the data processing section 1 sends a switching control signal to the clock switching section 2, selects the clock of the local oscillator 4, forms a frame within the intermediate relay device, and outputs it as data.

In this case, the local oscillator 4 is f/ (nl ・nt)
The clock oscillates at a frequency of f, is multiplied by (nl·nz) by a multiplier circuit, and the clock switching unit 2 switches the clock of frequency f.

[Problem that the invention seeks to solve]

Such conventional clock switching circuits have the disadvantage that when the clock frequency r becomes high, a circuit must be configured to perform high-speed processing switching.

The present invention aims to eliminate such drawbacks and provides a clock switching circuit that can perform switching at low speed.

[Means for solving problems]

The present invention provides a first terminal to which a first clock signal arrives;
A second terminal into which a second clock signal with a frequency that is an integer fraction of the frequency of the first clock signal is input, and a third terminal which outputs a third clock signal corresponding to the first clock, two inputs. In a clock switching circuit comprising a switching circuit having a terminal and one output terminal, a frequency dividing circuit inserted in a path between the first terminal and one input terminal of the switching circuit; a first multiplier circuit that is inserted in a path between the terminal and the other input terminal of the switching circuit and multiplies the second clock signal to a signal having a frequency equal to the frequency of the signal output from the frequency divider circuit; a second multiplier circuit inserted in a path between the output terminal of the switching circuit and the third terminal, and multiplying the signal output from the switching circuit to a signal having a frequency equal to the frequency of the third clock signal. It is characterized by

[For production]

One clock signal of frequency f is frequency-divided by n2. The other (nl·n,) clock signal having a frequency of f is multiplied by n2 times. one of two clock signals having a frequency of f/11 is selected by a switching circuit;
This clock signal is n.

A clock signal of frequency f is output after being multiplied by a factor of two.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings. 1st
The figure is a block configuration diagram showing the configuration of a clock switching circuit included in the intermediate relay device of the present invention.Normally, an input clock is selected in the clock switching unit 2, and this clock is input to the data processing unit 1. Be in sync with your data. If this information indicates an unattended state or a frame synchronization shift, a switching control signal is sent from the data processing section 1 to the clock processing section 2, and the clock on the local oscillation section 4 side is selected. This switching operation forms a frame within the intermediate relay device and outputs the data.

Here, this clock switching circuit includes a clock switching section 2.
A frequency divider circuit 5 that divides the input clock frequency is added to the front side of the clock, and a multiplier circuit 3b having a value similar to the frequency division ratio is added to the rear side of the clock, so that high frequency clock switching is avoided as much as possible and switching is performed by low-speed processing. . As a result, the multiplication ratio of the multiplier circuit 3a becomes n2 times.

〔Effect of the invention〕

As described above, the present invention has the frequency divider and multiplier circuits before and after the clock switching section, and therefore has the advantage that the clock switching section can be realized by a low-speed processing switching circuit.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional circuit. 1...Data processing section, #2...Clock switching section, 3
... Multiplier circuit, 4 ... Local oscillation section, 5 ... Frequency division circuit. Data output sample alL 凰shoulder 1 mouth

Claims (1)

[Claims] (1) A first terminal to which the first clock signal arrives, and a second terminal to which a second clock signal having a frequency that is an integer fraction of the frequency of the first clock signal is input, and corresponds to the first clock. In a clock switching circuit, the clock switching circuit includes a third terminal that outputs a third clock signal, and a switching circuit having two input terminals and one output terminal, wherein the first terminal and one input terminal of the switching circuit and a frequency dividing circuit inserted in a path between the second terminal and the other input terminal of the switching circuit to convert the second clock signal into a signal output from the frequency dividing circuit. A first multiplier circuit that multiplies a signal with a frequency equal to the frequency of the signal, and a first multiplier circuit that is inserted into a path between the output terminal of the switching circuit and the third terminal, and a signal that is output from the switching circuit at the frequency of the third clock signal. and a second multiplier circuit that multiplies a signal with a frequency equal to .