JPH04247735A - Frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To miniaturize the scale of circuit constitution and to attain reduction in cost by executing the replacement of a parallel signal by means of controlling the reset pulse of a frequency devision counter. CONSTITUTION:A reset pulse generation circuit 6 inputs the output signal of the frequency division counter 2 and a clock pulse, generates the four reset pulses with different timings, selects one from the four by a control signal from a synchronizing position detecting circuit 4 and outputs it to the frequency division counter 2. When the initial states FF1 and 2 of the counter 2 are both at L level, the four reset pulses outputted from FF5-8 are selected in a selector by the control signal from the circuit 4 and are outputted. The counter 2 receives the reset pulse and the timing of the output pulse which is reset and outputted to a serial/parallel conversion circuit 1 is changed. Thus, respective serial signal outputs outputted from the circuit 1 are controlled in such a manner that sequence is replaced so as to make correct position relation.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a frame synchronization circuit in a digital transmission system, and more particularly to a high-speed frame synchronization circuit that detects a frame synchronization pulse after parallelizing input data. .

0002

2. Description of the Related Art Conventionally, a frame synchronization circuit for high-speed digital signals of this kind has a configuration shown in FIG. FIG. 3 is a block diagram showing the circuit configuration of a conventional example. The high-speed digital signal on the digital transmission path is serially-parallel converted into a 1/N speed digital signal at the input of the frame synchronization circuit in order to reduce the speed of signal processing in subsequent stages. In FIG. 3, as an example, the input digital signal is serial-to-parallel converted to 1/4 by the serial-to-parallel conversion circuit 1, but the division ratio is not limited to this.

[0003] In order to detect the frame synchronization pattern of the digital signals that have been slowed down in parallel, a synchronization pattern detection circuit 3 consisting of a shift register is provided for each parallel signal.
Perform pattern matching. At this time, the output order of the input parallel signal, that is, the parallel signal output of the serial-to-parallel conversion circuit 1, may be cyclically changed by a number corresponding to the number of divisions depending on the initial conditions of the frequency division counter 2. This will be explained with reference to FIG.

FIG. 4 is a state explanatory diagram showing the state of parallel signals. [b]
(F628) h = (111101100010
If a digital signal with a 16-bit repeating pattern of 1000) is input, its parallel signal output shown as [c] will change from (state 1) to (state 4) indicates that four states exist. Now, if the parallel signal outputs in the correct positional relationship are numbered 1, 2, 3, 4 in order from the top, this order, that is, the positional relationship will be indefinite.

Now, in the synchronization pattern detection circuit 3, each of these parallel signals is compared with four systems of synchronization patterns in this example, and any of the matched synchronization patterns is used to detect the synchronization position for each parallel signal. Output to circuit 4. Synchronous position detection circuit 4
Then, the position of the parallel signal is detected from the synchronization pattern, and if there is an error, a control signal to correct the error is output to the channel selector 5. The channel selector 5 uses this control signal to switch the positions of the respective parallel signal outputs from the synchronization pattern detection circuit 3 to outputs 1 to 4 from the top to the correct positions. The frame information detected by the synchronization pattern detection circuit 3 is outputted as a frame synchronization pulse by the synchronization position detection circuit 4.

[0006]

[Problems to be Solved by the Invention] The conventional frame synchronization circuit described above performs synchronization pattern detection on each parallel signal series after serial-to-parallel conversion, but the output depends on the initial state of the frequency division counter. Since the positions of the output data are swapped, a channel selector is required to switch the position of each parallel signal output according to the detected synchronization pattern series, resulting in a problem that the circuit becomes large-scale.

[0007]

[Means for Solving the Problems] A frame synchronization circuit of the present invention includes a serial-to-parallel conversion circuit that inputs a high-speed digital signal and outputs a parallel signal, a frequency division counter that drives the serial-to-parallel conversion circuit, and a frequency division counter that drives the serial-to-parallel conversion circuit. Parallel signals to predetermined frame synchronization pattern
a pattern detection circuit that outputs a matched frame synchronization pattern for each of the parallel signals; and a pattern detection circuit that detects the position of the parallel signal corresponding to the matched frame synchronization pattern. a synchronous position detection circuit that outputs a control signal;
and a reset pulse generation circuit which inputs the control signal and outputs a reset pulse for changing the position of the parallel signal to the frequency division counter.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the circuit configuration of this embodiment. A synchronization pattern detection circuit 3 consisting of a shift register is connected to the output of the serial/parallel conversion circuit 1, and its synchronization pattern detection output is input to the synchronization position detection circuit 4, and its detection output, that is, the control signal output is Reset pulse generation circuit 6
By inputting the reset pulse output to the frequency division counter 2 and resetting it, the positions of the respective parallel signal outputs of the serial/parallel conversion circuit 1 are switched and controlled.

Among these, the constituent parts of the serial-to-parallel converter circuit 1, the synchronization pattern detection circuit 3, the synchronization position detection circuit 4, and the frequency division counter 2 have the same functions and operations as those explained in the conventional example, so they will be explained below. will be omitted, and the following will focus on the reset pulse generation circuit 6.

The reset pulse generating circuit 6 inputs the output signal of the frequency dividing counter 2 and the clock pulse, and generates four reset pulses with different timings. One is selected and output to the frequency division counter 2. Further, FIG. 2 is a timing chart diagram illustrating the operation of the reset pulse generation circuit 6. Now, as the initial state of the frequency division counter, FF1
, 2 are both at L level. At this time, four reset pulses outputted from FF5 to FF8 are selected and outputted by a selector according to a control signal from the synchronous position detection circuit 4.

The frequency division counter 2 receives this reset pulse, is reset, and the timing of the output pulse output to the serial/parallel conversion circuit 1 changes. As a result, the order of each parallel signal output from the serial-to-parallel conversion circuit 1 is changed, and the parallel signals are controlled so that they have a correct positional relationship.

0012

[Effects of the Invention] As explained above, the present invention realizes the replacement of parallel signals by a simple method of controlling the reset pulse of a frequency division counter, which is different from the conventional method using a channel selector that replaces the parallel signals themselves. Compared to this, the circuit configuration is smaller, which is effective in reducing the size and cost of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a timing chart diagram illustrating the operation of the reset pulse generation circuit 6. FIG.

FIG. 3 is a block diagram showing a circuit configuration of a conventional example.

FIG. 4 is a state explanatory diagram showing states of parallel signals.

[Explanation of symbols]

1 Serial-to-parallel conversion circuit 2 Divide counter 3. Synchronous pattern detection circuit 4 Synchronous position detection circuit 5 Channel selector 6 Reset pulse generation circuit

Claims (1)

[Claims] 1. A serial-to-parallel conversion circuit that inputs a high-speed digital signal and outputs a parallel signal, a frequency division counter that drives the serial-to-parallel conversion circuit, and a predetermined frame synchronization pattern to collate the parallel signal. a pattern detection circuit that outputs the matched frame synchronization pattern for each of the parallel signals;
a synchronization position detection circuit that detects the position of the parallel signal corresponding to the collated frame synchronization pattern and outputs a control signal; A frame synchronization circuit characterized by comprising a reset pulse generation circuit that outputs to a cycle counter.