JPS63245032A - High speed frame synchronizing system - Google Patents

Abstract

PURPOSE:To obtain the high speed operation and the reduction in the synchronization establishment time simultaneously by extracting a 1 time slot signal at a location corresponding to a frame synchronizing signal at a location corresponding to a frame synchronizing signal detected from a latched signal so as to take frame synchronization. CONSTITUTION:A frame synchronizing signal is detected in one frame by the parallel processing latching a (2n-1)-bit in one latch timing and using n-set of synchronization detection sections 11 to apply detection of synchronization from signals of n-bit deviated sequentially one by each by means of n-set of synchronization detection sections 11. Then a selector 13 is controlled by using number information of the synchronization detection sections 11 applying the detection of synchronization to extract signal by one time slot from data outputs by (2n-1) lines thereby obtaining an output with required frame synchronizing taken thereof. Moreover, the phase of the latch timing pulse is controlled by the selector and counters 3, 8 generating the latch timing pulse from the number information to obtain an output with the required frame synchronization taken. Thus, the high speed operation and the reduction in the synchronization establishment are obtained simultaneously.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 11 to 15) Problems to be solved by the invention Means for solving the problems (Figure 1) Working Examples (Figures 2 to 10) Effects of the Invention [Summary] On the receiving side of PCM communication in which frame synchronization signals consisting of n bits are concentrated in one frame and transmitted serially, a plurality of frame synchronization signals are transmitted serially. A synchronization detection unit is provided to convert the input serial signal into a parallel signal, detect frame synchronization signals from n-bit signals at different positions one bit at a time in the launched signal, and detect frame synchronization signals from the latched signals. Frame synchronization is achieved by extracting and outputting a signal of one time loft at a position corresponding to a synchronization detection section that detects the signal, thereby simultaneously realizing high-speed operation and shortening of synchronization establishment time.

[Industrial application field]

The present invention relates to a frame synchronization method for frame synchronizing received data, and particularly to a high-speed frame synchronization method that is capable of high-speed operation and has a short synchronization establishment time.

In PCM communication, in order to enable the receiving side to receive the transmitted data correctly, a frame synchronization signal is superimposed on the transmitted data and sent, and the receiving side identifies the phase of the received data based on this frame synchronization signal. Frame synchronization methods are commonly used.

In such a frame synchronization method, it is desired that the synchronization operation can be performed as fast as possible, and that the time required to establish synchronization is short.

[Conventional technology]

Conventionally, two methods have been used as frame synchronization methods, as described below. In the following, the frame structure is assumed to be 1 frame = m time slots (TS), 1 time loft = n bits, and the frame synchronization signal FSYN is applied to the first time loft as shown in Fig. 11.
Assume that C is centrally placed.

FIG. 12 shows the configuration of the first conventional example,
This example shows a case where synchronization detection is performed bit by bit.

Further, FIG. 13 shows a time chart of each part signal in this case.

In FIG. 12, input serial data consisting of fo bps is converted to fOHz in a serial/parallel converter (S/P) section 1.
is converted into serial/parallel signals of n bits corresponding to one time slot by the clock of f0, is latched by the clocks of fo and fo/nHz in the launch section 2, and is converted into n-bit parallel signals corresponding to one time slot.
Produces output data at o/n bps.

On the other hand, the synchronization detection unit 5 compares the n-bit parallel signal from the serial-to-parallel conversion unit 1 with a predetermined frame synchronization signal pattern.
When they match, a reset signal is generated to reset counters 3 and 4. Here, the counter 3 is a bit counter, and counts the number of bits of input data using a fo Hz clock, and calculates fo/n bp.
It generates a pulse of s, that is, an output indicating the division of time slots. Counter 4 is a time slot counter, which counts the fo/n pulses of counter 3.
A pulse of fo/nm bps, that is, a clock indicating a frame break is generated.

In accordance with the output of the counter 4, the synchronization protection section 6 checks whether a coincidence is detected again in the synchronization detection section 5 when the next frame synchronization signal arrives.

This is repeated multiple times as backward protection, and when the frame synchronization signal pattern is detected a predetermined number of times in succession,
Determine the establishment of frame synchronization and frame synchronization pulse F, 5
Output ync.

In FIG. 13, each register output SR1+"-+5Rn-1+SRn in the serial/parallel converter 1 has a frame synchronization signal pattern PL-+Fr1 as shown by a large solid line.
-1+Fn appears, a reset signal is output, and the counter 3. It is shown that counter 4 is reset.

FIG. 14 shows the configuration of the second conventional example,
This example shows a case where synchronization detection is performed for each time slot.

Further, FIG. 15 shows a time chart of each part signal in this case.

In FIG. 14, the serial/parallel converter 1, luff 2, and counter 3 constitute a high-speed section, and the input serial data consisting of fo bps is converted into n pints corresponding to one time slot in the serial/parallel converter 1 by the foHz clock. It is serial-parallel converted into parallel signals and latched in latch 2 by fo and the fo/n Hz clock of counter 3 to produce output data of fo/n bps.

Counter 3 is a high-speed counter that counts the number of bits of input data using a fo Hz clock.
It generates o/n bps pulses, that is, clocks indicating time slot divisions.

On the other hand, the synchronization detection section 7. Counter 8. The synchronization protection section 9 constitutes a low-speed section, and the synchronization detection section 7
The bit parallel signal is compared with a predetermined frame synchronization signal pattern to detect a match.

When the synchronization detection section 7 does not detect a match, the synchronization protection section 9 sends a shift pulse to the counter 3 to shift the count by 1 bit, thereby shifting the launch timing in the latch section 2 by 1 bit. The synchronization detection unit 7 performs coincidence detection again in the next frame. By repeating such operations, synchronization detection is continued while sequentially shifting the latch timing one bit at a time. When the synchronization detection section 7 detects a match with the frame synchronization signal pattern, the synchronization protection section 9 generates a reset signal and resets the counter 8. The counter 8 is a low-speed counter that counts the fo/n pulses of the counter 3 and generates fo/nm bps (7) pulses, that is, a clock indicating a frame break.

After that, it is checked whether or not coincidence detection is performed multiple times as backward protection, and when a frame synchronization signal pattern is detected a predetermined number of times in succession, it is determined that frame synchronization is established and a frame synchronization pulse F, 5sync is output. do.

In FIG. 15, each register output LR1+'-+LRn-1, LRn in the latch unit 2 is sequentially shifted one bit at a time by a shift pulse 2, and as shown by the large solid line, the frame synchronization signal pattern F1. -・-IFn-
It is shown that when 1+Fn appears, a reset signal is output and the counter 8 is reset.

[Problem that the invention seeks to solve]

In the conventional method shown in FIGS. 12 and 13, the synchronization detection section detects the frame synchronization signal at the transmission line speed (FO bps), and if there is no error in the transmission signal, one frame time This has the advantage that the frame synchronization signal can always be captured within the same period, and synchronization can be established quickly.

However, in this method, it is necessary to perform a series of processes such as serial-to-parallel conversion, synchronization detection, and counter reset within one bit, and high-speed operation is required for each component. In the case of this method, since it includes a loop that requires high-speed operation,
The operating speed in this method is expected to be 1/2 or less of the maximum operating speed of the device used (especially flip-flops).

In the conventional system shown in FIGS. 14 and 15, it is the serial/parallel converter 1 that requires high-speed operation. Lunch part 2
Since only the high-speed section consisting of the and counter 3 and the low-speed section including the loop system need only operate at the time slot speed, the operable speed relative to the maximum operating speed of the device used is improved.

However, in this method, it takes a long time to detect a frame synchronization signal, and in the worst case, it requires n frame time. Therefore, it takes a long time to establish synchronization, and when switching transmission lines, etc., the ripple effect on the terminal equipment at the end is large, which becomes a problem especially when multi-stage connections are made.

[Means for solving problems]

The present invention is intended to solve the problems of the prior art, and has the basic configuration shown in FIG. In a frame synchronization method on the receiving side of PCM communication in which a part of the PCM communication is centrally arranged and transmitted serially, a launch means 101 and a parallel synchronization detection means 102 are used.
and output selection means 103.

Launch means 01 converts an input serial signal into a parallel signal and latches it.

The parallel synchronization detection means 102 has a plurality of synchronization detection sections, and includes latch hands 1. Frame synchronization signals are detected from n-bit signals at sequentially different positions one bit at a time in the signal latched by the tk 101.

The output selection means 103 extracts and outputs a signal of one time loft at a position corresponding to the synchronization detection section that detected the frame synchronization signal from the signal latched by the launch means 101.

Furthermore, the output selection means 103 is controlled by the latch means 10 based on the control from the synchronization detection section that has detected the frame synchronization signal.
The latch means 10 is a selector means for selecting a signal of one time slot from a plurality of output lines of the latch means 10 based on control from a synchronization detection section that detects a frame synchronization signal.
This is a clock phase selection means for changing the latch timing in 1.

[For production]

In the method of the present invention, 2n
Frame synchronization signal detection within one frame is made possible by parallel processing in which -1 bit is latched and n synchronization detection units sequentially perform synchronization detection from n-bit signals shifted by one bit.

Then, the number of the synchronization detection section in which synchronization detection was performed among the n synchronization detection sections is stored in the memory, and the selector is controlled using this information to output one time slot's worth of signals from 2n-1 data outputs. By extracting, the desired frame-synchronized output is obtained.

Alternatively, the phase of the latch timing pulse is controlled by the selector based on the information of the number of the synchronization detecting unit in which the synchronization detection was performed, which is stored in the memory, to obtain a desired frame-synchronized output.

Alternatively, the phase of the launch timing pulse can be controlled by shifting the count of the counter that generates the latch timing pulse based on the information of the number of the synchronization detection unit that has performed the synchronization detection stored in the memory, and controlling the phase of the launch timing pulse to generate the desired frame. Obtain synchronized output.

According to the configuration of the present invention, since there is no loop system in the high-speed section and delay time is not a problem, it is possible to operate up to the maximum operating speed of the device used.

On the other hand, the frame synchronization detection section having a loop system has an operating speed of 1/n, is not affected by the maximum operating speed of the device used, and detects frame synchronization through parallel processing, which shortens the frame synchronization establishment time.

〔Example〕

FIG. 2 shows one embodiment of the present invention.
The same parts as in FIG. 4 are indicated by the same numbers, 11 is a parallel synchronization detection section, 12 is a synchronization control section, and 13 is a selector.

FIG. 3 shows the counter 8. in FIG. Synchronization protection section9. Parallel synchronization detection section 11. This figure shows an example of the configuration of a synchronization processing section including a synchronization control section 12 (input key) 4.

Further, FIG. 4 is a time chart showing the signals of each part in FIGS. 2 and 3, and illustrates the case where the number of bits constituting one time slot is 11 w 3.

Serial-to-parallel converter 1. Latch part 2. The configuration of the high-speed section consisting of the counter 3 is the same as that shown in Fig. 14, but the serial-to-parallel converter 1 and the latch section 2 consist of 2n-1 bits, and input data of fo bps is processed by a clock of fo Hz. 2n-
Generates 1-bit parallel output.

As shown in FIG. 3, the parallel synchronization detection section 11 consists of n-bit synchronization detection sections #1 to #n of ntm, and sequentially detects n bits shifted by 1 bit from a 2n-1 bit parallel signal. The signals are taken in and sequentially compared with a predetermined frame synchronization signal pattern, and when a match is detected in any of the synchronization detectors, a match pulse is generated.

In the synchronization control section 12, the OR circuit OR takes the logical sum of the coincidence pulses of the n synchronization detection sections and generates an output, thereby resetting the counter 8.

At the same time, a strobe signal is generated and the number of the synchronization detector that generated the coincidence pulse is written into the control memory MEM.

The synchronization protection unit 9 checks whether a match is detected again in the parallel synchronization detection unit 11 when the next frame synchronization signal arrives according to the output of the counter 8. At this time, the selector SEL selects the control memory MEM. By being controlled by the output, the output of the synchronization detector that detected the previous match is selected, so matching can be detected for the same time slot. In the synchronization protection section 9, this is repeated a plurality of times as backward protection, and when a frame synchronization signal pattern is detected consecutively a predetermined number of times, it is determined that frame synchronization has been established and a frame synchronization pulse F, 5sync is output.

At the same time, the synchronization control unit 12 writes the control memo 'J M E
The selector 13 is controlled by the output of M, and the launch section 2
From the 2n-1 parallel signal outputs, the parallel synchronization detection unit 11
The n signals corresponding to the synchronization detecting sections in which a match is detected are selected. This causes the selector 13 to
/n bps of output data.

In FIG. 4, when the serial-to-parallel converter 1 and the launch unit 2 are composed of 5 bits corresponding to nm3, frame synchronization signal patterns F1. F2. It is shown that the #2 synchronization detector detects F3, thereby resetting the counter 8, and writing the number (0, 1, 0) of the synchronization detector in the control memory MEM by the strobe signal. The selector 13 thereby selects and outputs the outputs of the registers LRI to LR3 of the latch section 2.

In the method shown in the embodiments of FIGS. 2 to 4, the parallel synchronization detector is effective only during the first detection of the frame synchronization signal from the free run state, and when there is no transmission path disturbance, the parallel synchronization detector is effective only for the first frame synchronization signal. Since the frame synchronization signal can always be detected within one frame, the synchronization establishment time is shortened. After the synchronization is detected, the time slot 7) where the frame synchronization signal exists in the signal after the latch is known by being specified by the control memory MEM, and therefore the necessary n data outputs can be obtained from the 29-1 parallel signal. can be extracted.

In this embodiment, one time slot is n bits, and the frame synchronization signal is also n bits, but the number of frame synchronization signals is shifted by n, and the number of signal lines for synchronization detection is set to 2n' -1. ' If -1<n, set the number of latches to n2n' If -1≧n, set the number of latches to 2n'
Similar results can be obtained by setting -1.

FIG. 5 shows another embodiment of the present invention, in which the same parts as in FIG. 2 are designated by the same numbers, and 2^, 2B
are latch parts each consisting of n bits, and 2C is a selector. In the embodiment shown in FIG. 5, the serial-to-parallel converter 1 consists of n bits, and the n-bit launch parts 2A,
2B are provided in parallel, and fo/ from counter 3 is
2n clock φ1. N bits are alternately launched in response to φ2, and the launch parts 2A and 2B are sent via the selector 2c.
2n-1 bits of parallel output is generated by reading the outputs of 2n-1 bits in parallel. The subsequent processing is the same as in the case of FIG. 2, and frame synchronization operations can be performed in the same manner.

FIG. 6 shows another embodiment of the present invention, in which the same parts as in FIG. 2 are designated by the same numbers, and 14 is a selector.

FIG. 7 shows counter 8. in FIG. Synchronization protection section9. Parallel synchronization detection section 11. An example of the configuration of a synchronization processing section including a synchronization control section 12 is shown.

Further, FIG. 8 is a time chart showing the signals of each part in FIGS. 6 and 7, and illustrates the case where the number of bits nsw constituting one time slot is 3.

Serial-to-parallel converter 1. Latch part 2. The configuration of the high-speed section consisting of the counter 3 is the same as that shown in FIG.
The difference is that it changes from φn to φn. The serial/parallel converter 1 converts fo bps input data to fo Hz
The latch unit 2 latches the output of the serial/parallel converter 1 at the time slot period using the fo/nHz clock output from fO and the selector 14, and performs 2n-1 bit parallel conversion. Generate output.

The parallel synchronization detection unit 11 has the same specific configuration as the embodiment shown in FIG. B, 7
The signals of n focuses shifted by 1 are taken in and sequentially compared with a predetermined frame synchronization signal pattern, and when a match is detected in any of the synchronization detectors, a match pulse is generated.

In the synchronization control section 12, the OR circuit OR takes the logical sum of the coincidence pulses of the n synchronization detection sections and generates an output, thereby resetting the counter 8.

At the same time, a strobe signal is generated and the number of the synchronization detector that generated the coincidence pulse is written into the control memory MEM.

The synchronization protection unit 9 checks whether a match is detected again in the parallel synchronization detection unit 11 when the next frame synchronization signal arrives according to the output of the counter 8. At this time, the selector 14 selects the output from the memory MEM. Under the control of the selector control output, a launch pulse is generated in the time slot in which the previous match was detected. This latch timing signal is given to, for example, the first synchronization detection section #1, and thereafter the frame synchronization signal is detected by the synchronization detection section #1.

The synchronization protection unit 9 looks at the coincidence detection in the synchronization detection unit #1, checks multiple detections as backward protection, and determines that frame synchronization has been established when the frame synchronization signal pattern force < + * is issued consecutively a predetermined number of times. and frame synchronization pulse F,
Outputs 5sync.

Output data of fo/nbps is generated by extracting n signals corresponding to synchronization detection section #1 in parallel synchronization detection section 11 from the 21-1 parallel signals of latch section 2.

In FIG. 8, when the serial-to-parallel converter 1 and the launch unit 2 are composed of 5 bits corresponding to nwa 3, the frame synchronization signal patterns PI, F2 . It is shown that the #2 synchronization detector detects F3, thereby resetting the counter 8, and writing the number (0, 1, 0) of the synchronization detector in the control memory MEM by the strobe signal. The selector 14 thereby controls the latch timing for the latch unit 2 so that the signal of the required time slot is output to the registers LRI to LR3 of the latch unit 2. In the method shown in the embodiments of FIGS. 6 to 8, the parallel synchronization detection section is effective only during the time period when the frame synchronization signal is first detected from the free run state, and if there is no transmission path error, the parallel synchronization detection section Since the frame synchronization signal can be detected without fail, the synchronization establishment time is shortened. After synchronization is detected, the latch timing specified by control memory MEM becomes valid, and registers LRI to LR
The desired output data is stored in 3, and only the first synchronization detection section becomes operational.

In this case, one time slot is also n bits, and the frame synchronization signal is also n bits, but the number of frame synchronization signals is n' bits, and the number of signal lines for synchronization detection is 2n'.
-1, and if 2n'-1<n, the number of latches is n2n' -1
When ≧n, similar results can be obtained even if the number of latches is set to 2n'-1.

FIG. 9 and FIG. 10 each show still another embodiment of the present invention.

In FIG. 9, the same parts as in the embodiment of FIG. 6 are indicated by the same numbers, and 15 is a shift pulse generating section.

In the embodiment of FIG. 9, the output clock f of the counter 3 is selected by the selector 14 in the embodiment of FIG.

Instead of changing the phase of /n, a shift pulse generating section 15 controlled by the control output of the synchronization control section 12 is provided, and by shifting the count number of the counter 3 by the output pulse, the latch section 2 It is designed to control the latch timing in
The same operation as the embodiment shown in FIG. 6 can be realized.

In FIG. 10, the same parts as in the embodiment of FIG. 9 are designated by the same numbers, and the launch parts 2A, 2B
, the configuration of the selector 2C is the same as that described in the embodiment of FIG.

In the embodiment shown in FIG. 10, latch parts 2A, 2B and a selector 2 are used instead of the latch part 2 in the embodiment shown in FIG.
A clock φ1.C of fo/2n from the counter 3 is provided. By alternately latching n bits at a time according to φ2 and reading the outputs of the latch sections 2A and 2B in parallel via the selector 2C, a parallel output of 2n-1 bits is generated. The subsequent processing is performed in the same manner as in the case of FIG. 9, and frame synchronization operations can be performed in the same manner.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of synchronization detection sections are provided for a signal obtained by latching an input signal at high speed,
Frame synchronization is achieved by detecting a frame synchronization signal from the latched signal and extracting and outputting the signal of one time slot at the position corresponding to the synchronization detection section that detected the frame synchronization signal. Obstacles to high-speed operation based on delay time in the high-speed loop system of can be realized simultaneously.

The method of the present invention is effective for LSI implementation, and since the configuration of the high-speed section is simplified, it becomes possible to perform high-speed frame synchronization processing near the maximum operating speed of the device, and since there are fewer high-speed operating sections, power consumption is reduced. Ru.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an example of the configuration of the synchronization processing section in FIG. 2, and FIG. 5 is a diagram showing another embodiment of the present invention, FIG. 6 is a diagram showing another embodiment of the present invention, and FIG. 7 is a time chart showing signals of each part in FIGS. 2 and 3. FIG. 8 is a time chart showing the signals of each part in FIGS. 6 and 7; FIGS. 9 and 10 are each another embodiment of the present invention. FIG. Fig. 11 is a diagram illustrating the frame structure, and Fig. 12 is a diagram illustrating the frame structure.
13 is a diagram showing the time chart of each part signal in the conventional example of FIG. 12, FIG. 14 is a diagram showing the configuration of the second conventional example, and FIG. It is a figure which shows the time chart of each part signal in the conventional example of a figure. 1-Serial to parallel conversion (S/P) section 2, 2A, 2B--Latch section 3.8--Counter 9--Synchronization protection section 11...-Parallel synchronization detection section

Claims (3)

[Claims] (1) In a frame synchronization method on the receiving side of PCM communication in which a frame synchronization signal consisting of n bits or a part of the frame synchronization signal is concentrated in one frame and transmitted serially, the serial signal is converted into a parallel signal. Parallel synchronization consisting of a latch means (101) that converts and latches, and a plurality of synchronization detectors that detect the frame synchronization signal from n-bit signals at sequentially different positions one bit at a time in the latched signal. 1 at a position corresponding to the detection means (102) and the synchronization detection section that detects the frame synchronization signal from the latched signal.
A high-speed frame synchronization system characterized by comprising an output selection means (103) for extracting and outputting a time slot signal. (2) A selector in which the output selection means (103) selects a signal of one time slot from the plurality of output lines of the latch means (101) based on control from a synchronization detection section that has detected a frame synchronization signal. A high-speed frame synchronization method according to claim 1, characterized in that the method is a means for high-speed frame synchronization. (3) The output selection means (103) is a clock phase selection means that changes the latch timing in the latch means (101) based on control from a synchronization detection section that detects a frame synchronization signal. A high-speed frame synchronization method according to claim 1.