JPH01188050A - Timing system - Google Patents

Abstract

PURPOSE:To attain retiming of an input data by using a digital signal to initialize the internal state, retarding an output signal applying 1/2 frequency division to a clock signal by a half clock of the clock signal. CONSTITUTION:Clock signals represented by output signals c, c' of an inverter circuit 106 have a different phase from clock signals b, b' of a frequency 2f0 inputted from a clock input line 102 by T/4. Clock signals c,c' are used to segment output signals d, d' of a 1/2 frequency division circuit 104 by a D-F/F 105. That is, clock signals e, e' are signals with a retarded phase by T/4 in comparison with the output signals d, d'. The rising of the clock signals e, e' appears at a phase point retarded by T/4-3T/4 from the change point of the input data signal (a). Thus, the clock signals e, e' are used to apply retiming to the input data signal (a) without error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing method, and particularly to a timing method used in a digital transmission system such as a backbone transmission system, a public network, or a subscriber system.

[Conventional technology]

The progress of transmission technology using optical fiber as a transmission medium is remarkable, and the amount of information transmitted is several hundred Mbps.
Transmission of up to several Gbps is becoming possible. In this high-speed transmission system, an external timing method is considered as one method for timing transmission data.

FIG. 3 is a block diagram showing a configuration example of a conventional external timing system used in the digital transmission system. In the figure, 301 is a data input line, 302 is a clock input line, 303 is an identification circuit, 304 is a selector circuit, and 30
5 is a control signal input line, 3061 to 3063 are gates, 3
07 is a data output line, and 308 is a clock output line.

Here, the clock signal input from the clock input line 302 and the data signal input from the data input line 301 are as follows.
Although they have the same repetition period (To=1/fo),
-ffi is not necessarily phase synchronized, so the data signal cannot be immediately retimed using this clock signal.

Therefore, this input clock signal is passed through gates 3061 to 3o63 having unique gate delays to generate four-phase clock signals, and the selector circuit 304 which receives the generated four-phase clock signals as input controls the control. 4 based on the control signal input from the signal input line 305.
Select one phase clock signal from the phase clock signals.

This selected clock signal becomes the long signal of the identification circuit 303. Using this selected clock signal, the identification circuit 303 identifies and retimes the data signal input from the data input line 301.

In this way, in the third [21st circuit], the clock signal used for retiming is one of the four-phase clock signals.
Since the phase can be selected and used, even if the clock signal input from the clock input line 302 and the data signal input from the data input line 301 are not phase synchronized, this data signal can be used. It becomes possible to perform retiming without error.

[Problem that the invention seeks to solve]

In the conventional external timing method described above, four-phase clock signals are generated by non-logical operations using gates 306 to 3063 having inherent gate delays, and one phase is extracted from these four-phase clock signals. Since the input data is retimed, the gates 306 to 306 .
The gate delay 11 that the gate has is an important factor in data retiming, and the gate ffi extension had to be set at 2g depending on the repetition frequency (fo) of the input data.

An object of the present invention is to provide a simple circuit configuration that solves these problems, eliminates the need to generate a clock signal for data retiming using non-logical operations, and provides timing independent of the repetition frequency of input data. The goal is to provide a method.

[Means for solving problems]

The timing method of the present invention is a timing method in which a digital signal and a clock signal having a repetition frequency twice that of the digital signal are supplied, and the internal state is initialized using the digital signal, and the frequency of the clock signal is divided by two. a delay circuit that delays the output signal of the frequency divider by half a clock of the clock signal; and a retiming means that retimes the digital signal using the output signal of the delay circuit. have.

〔Example〕

Next, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing an embodiment of the timing method of the present invention, and FIG. 2 is a time chart showing timing waveforms of various signals in FIG. 1.

In FIG. 1, alphabetical characters a, b, c, d, 1), and f indicate signal positions of timing waveforms in the timing chart of FIG. 2, 101 is a data input line, 102 is a clock input line, and 103 is a clock input line. D flip-flop (D-F/
104 is an identification circuit consisting of a T flip-flop (T
-F/F), 105 is a D-F/F,
106 is an inverter circuit, 107 is a data output line, 10
8 is a clock output line. Here, clock input line 10
The clock signal input from 2 is the data input line 10]
The repetition frequency is twice that of the data signal input from <
2 f o = 1/2 T )'.

The divide-by-2 circuit 104 resets its internal state at the rising edge of the data signal input from the data input line 101, and divides the clock signal having a frequency component twice that of the data signal by two. On the other hand, a clock signal with a repetition frequency of 2fo input from the clock input line 102 is phase-inverted by an inverter circuit 1.06. Using this phase-inverted clock signal, the D-F/F 105 is a divide-by-2 circuit 1.
The clock signal of repetition frequency fo which is the output signal of 04 is punched out. Furthermore, the identification mouth ri? 1103 is this D-
Repetition frequency f which is the output of F/F 105. The data signal input from the data input line 101 is identified using the clock signal of , and the retimed data signal is output to the data output line 07. Here, as a method for generating a clock signal with a repetition frequency of 2fo inputted from the clock input line 102, there is a method having a clock signal oscillator with a repetition frequency of 2fo as a system clock, or a method with a repetition frequency of f as a system clock. It has a clock signal of
One possible method is to generate a clock.

In timing charts 1 to 1 in FIG. 2, point A is the start time of this timing chart. a is a data signal input from the data input line 101, 1), ' l)
' is a clock signal input from the clock input line 102, c, c' are output signals of the inverter circuit 106, d,
d' is the output signal of the divide-by-2 circuit 104, e, e' are the clock signals output from the clock output line 108, f, f'
is the timing waveform of the data signal output from the data output 107. For the clock signals S and b', the phase relationship between the data signal input from the data input line 101 and the clock signal input from the clock signal input line 102 is different.

A process of identifying and retiming the data signal input from the data input line 101 without error using the clock signal of the repetition frequency fo which is the output signal of the D-F/F 105 using FIGS. 1 and 2. I will explain about it.

The timing charts for the signals a, b, c, d, e, and f are for the case where the rising point of the input clock signal is slightly earlier in time than the changing point (rising, falling point) of the input data signal a. ,b'.

The timing charts c', d', e', and f' are for cases where the rising point of the input clock signal is slightly later in time than the changing point of the input data signal a. In either case, the internal state of the divide-by-2 circuit 104 is reset at the rise of the input data signal a, so the state of the clock signal that is the output of the divide-by-2 circuit 104 is uniquely determined, and the output signal d A clock signal having a repetition frequency fo, which is obtained by dividing the input clock signals S and b' by two, is outputted as shown by and d'. Clock signals indicated by output signals C and e' of the inverter circuit 106 are clock signals S and B having a repetition frequency of 2fo inputted from the clock input line 102.
' has a phase difference of T/'4. Using these clock signals C and e', the DF/F 105 punches out the output signals d and d' of the divide-by-2 circuit 104. clock signals e and e
The timing chart '' shows the output signal of this DF/FLO5. That is, clock signals e and e
' is a signal whose phase is delayed by T/4 compared to the output signals d and d'. The rising edge of these clock signals e and e' always corresponds to the input data signal a input from the data input line 101.
Since it appears at a phase point delayed by T/4 to 3T, /4 from the change point of , it is possible to retiming the input data signal a without error using these clock signals e and e'.

The above has described a timing method using a clock signal having an edge-back frequency component twice that of the input data signal, but the present invention is not limited to these combinations; On the other hand, the same effect can be expected even when a clock signal having a repetition frequency component that is an integer multiple is used. Furthermore, various methods such as using a frequency doubler can be considered as a method of generating a clock signal that is an integer multiple.

〔Effect of the invention〕

As explained above, according to the timing method of the present invention,
There is an effect that input data can be retimed by using simple logical operations without depending on the repetition frequency of input data.

The present invention relates to a timing method in a digital transmission system, and is expected to be applied to optical fiber transmission systems, which will become even faster and larger in capacity in the future.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the timing method of the present invention, FIG. 2 is a timing chart showing timing waveforms of various signals in FIG. 1, and FIG. 3 is a configuration example of a conventional timing method. It is a block diagram. 101,301...data input line, 102,302...
... Clock input line, 103, 303. ...Identification circuit, 104...2 frequency divider circuit, 105...D-F/F,
106... Inverter circuit, 107, 307... Data output line, 108, 308... Clock output line, 3
04...Selector circuit, 305...Control signal input line, 3061-3063...Gate. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] In a timing system in which a digital signal and a clock signal having a repetition frequency twice that of the digital signal are supplied, a divide-by-2 circuit that initializes an internal state using the digital signal and divides the frequency of the clock signal by two;
Timing characterized by comprising: a delay circuit that delays the output signal of the divide-by-2 circuit by half a clock of the clock signal; and a retiming means that retimes the digital signal using the output signal of the delay circuit. method.