JPH10247903A - Bit synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bit synchronization circuit that has provision for a high speed burst signal where reception data are scatteringly produced and the input timing is unstable without employing a high speed clock over a reception data speed and has excellent tracking performance with respect to phase fluctuation in consecutive signals. SOLUTION: The bit synchronization circuit 10 is provided with a control means 50 consisting of delay circuits 11 delaying a system clock, a phase comparison pulse generating circuit 12, phase selection circuits 13, 14, a phase compactor circuit 15, a phase discrimination circuit 16 and a latch circuit 17, the delay circuits 11 produce polyphase system clocks, the phase comparison pulse generating circuit 12 generates a pulse at a change point of reception data and at a rise point of the polyphase clocks, the control means 50 uses the generated pulse to make phase comparison and the result of comparison controls a clock phase for data segmentation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit, and more particularly, to a bit synchronization circuit capable of responding to a burst signal input and capable of high-speed operation with high tracking capability to a phase variation of a continuous signal.

[0002]

2. Description of the Related Art In a PDS (Passive Double Star) system, a plurality of subscriber line terminating units (ONUs) are opposed to a subscriber line terminating unit (SLT) installed on a station side. In this case, the two are connected by a star coupler.

In this high-speed PDS system or the like, a bit synchronization circuit is widely used as a receiving circuit when receiving and reproducing high-speed data.

[0004] Conventional bit synchronization circuits of this type include:
For example, a method of extracting a clock timing from received data (Reference: Matsumoto, et al., "Prototype of Low-Voltage (3V) Serial Interface Data Reproducing Circuit" All Fall Meeting 1994, B-420), a high-speed clock for received data Method of importing by using (Reference: Iwamura, Ashi “High-speed P
Bit Synchronization Circuit for Burst Transmission in DS System "IEICE Technical Report SSE95-83, IN95-54, CS
95-103) and the like.

A method of extracting timing from received data is to extract clock timing from received data,
The receiving data is taken in by the extracted clock. Since the data timing matches the timing of the taking clock, the data can be reproduced without error. The method using a high-speed clock generates a multi-phase clock by using a clock that is faster than the received data rate, and performs accurate data reproduction by selecting the clock with the most suitable phase for data capture. It is.

[0006]

However, in such a conventional bit synchronization circuit, when the timing is extracted from the received data, when the timing is extracted from the received data, it takes a long time to extract the timing. However, if the same code is continuously input, there is a problem that accurate timing extraction cannot be performed. Therefore, the received data must be continuous data. For this reason,
In a burst signal in which input data occurs sporadically and the input timing is indefinite, it is difficult to cope with high-speed data due to problems such as the time required for timing extraction and the same code continuous section generated between data. was there.

Further, it takes time to extract timing even for a sudden phase change between continuous signals in a signal containing many jitter components, so that it is difficult to have a good tracking characteristic. Further, a narrow band-pass filter, a PLL, or the like is usually used for timing extraction. However, there are many configurations using analog circuits, and there are many aspects that are not suitable for miniaturization.

On the other hand, the method using a high-speed clock requires a high-speed clock that exceeds input data in the device.
Therefore, when handling high-speed data, a further high-speed signal is required, and the higher the data communication speed, the more difficult it becomes to realize.

The present invention can cope with a high-speed burst signal in which received data sporadically occurs and the input timing is uncertain, without using a high-speed clock that exceeds the reception data speed, and is suitable for a phase fluctuation in a continuous signal. It is an object of the present invention to provide a bit synchronization circuit having excellent followability.

[0010]

SUMMARY OF THE INVENTION A bit synchronization circuit according to the present invention is a bit synchronization circuit for changing received data to a system clock. A pulse generation means for generating a pulse at the transition point and a rising point of the polyphase clock multiplied by the delay means, and a phase comparison is performed using the pulse generated by the pulse generation means. And control means for controlling the phase.

A bit synchronizing circuit according to the present invention is a bit synchronizing circuit for changing received data to a system clock. The bit synchronizing circuit includes a delay means for delaying the received data to make it multi-phase, and a change point of the system clock and the delay means. Pulse generating means for generating a pulse at the rising point of the polyphased polyphase data, and control means for performing a phase comparison using the pulse generated by the pulse generating means and controlling a data phase for data punching based on the comparison result And is configured.

In the phase comparison by the control means, a phase comparison A in which a data change point pulse generated at a change point of received data is punched out by a clock rising pulse having a selected phase and a clock rising pulse is punched out by a data change point pulse. The phase comparison B may be used.

The control means determines that the setup time may not be satisfied if the phase comparison A misses the data change point pulse by the clock rising pulse, and determines whether the phase comparison B has the clock. If the rising pulse is missed by the data change point pulse, it may be determined that the hold time may not be satisfied.

In addition, the above-mentioned control means, based on the result of the phase comparison A with respect to the currently selected clock phase,
If it is determined that the setup time may not be satisfied, control is performed to increase the setup time by delaying the phase of the selected clock, and the hold time may not be satisfied based on the result of the phase comparison B. When it is determined that the hold time is increased by advancing the phase of the selected clock, the setup / setup is performed based on the results of the phase comparison A and the phase comparison B.
If it is determined that both hold times are satisfied, control may be performed so as to hold the currently selected phase.

When the control means determines that there is a possibility that the setup time may not be satisfied with respect to the currently selected data phase based on the result of the phase comparison A, the control means delays the phase of the selected data. Control to increase the setup time, and if it is determined that the hold time may not be satisfied based on the result of the phase comparison B, the control to increase the hold time is advanced by advancing the phase of the selected clock. If it is determined that both the setup / hold times are satisfied based on the results of the phase comparison A and the phase comparison B, control may be performed so as to hold the currently selected phase.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A bit synchronization circuit according to the present invention
It can be applied to a bit synchronization circuit corresponding to burst transmission in a high-speed PDS system.

FIG. 1 is a circuit diagram showing a configuration of a bit synchronization circuit according to a first embodiment of the present invention, and shows an example in which a system clock is used in four phases.

In FIG. 1, a bit synchronizing circuit 10 includes a delay circuit 11 (delay means) including three delay circuits 1 to 3 having different delay times, a phase comparison pulse generation circuit 12 (pulse generation means), Phase selection circuit 1
3, 14 (phase selection circuits 1 and 2), phase comparison circuit 15,
It comprises a phase determination circuit 16 and a latch circuit 17.

The phase selection circuits 13 and 14, the phase comparison circuit 15, the phase determination circuit 16 and the latch circuit 17 perform a phase comparison using the generated pulses as a whole, and determine a clock phase for data punching based on the comparison result. The control means 50 for controlling is constituted.

As input, the received data and the system clock used in the receiving device are used. The system clock is input to delay circuits 1 to 3.

The delay circuits 1 to 3 delay １ ／, ２ and ／ cycle of the system clock, respectively. The generated four-phase clock is input to the phase selection circuit 14 (phase selection circuit 2) and the phase comparison pulse generation circuit 12. The received data is also input to the phase comparison pulse generation circuit 12.

The phase comparison pulse generation circuit 12 generates four-phase clock rising pulses 1 to 4 based on the generated four-phase clock and system clock.

The above-mentioned phase selection circuit 13 (phase selection circuit 1)
Is 4 which has been pulsed by the phase comparison pulse generation circuit 12.
One of the phase clock pulses is selected, and the selected clock pulse is output to the phase comparison circuit 15.

The phase comparison circuit 15 compares the phase of the pulsed received data with the selected clock pulse selected by the phase selection circuit 13, and outputs the comparison result to the phase determination circuit 16 as a phase determination result.

The phase determination circuit 16 is provided with an UP / DOWN
It is configured by a counter, performs phase determination based on the phase determination result, performs phase control of a selected clock described later, and outputs a phase selection signal to the phase selection circuits 13 and 14.

The phase selection circuit 14 selects one of the input four-phase clocks and outputs it as a latch clock.

The latch circuit 17 includes a phase selection circuit 14
The input data is latched by the output clock from the CPU and output as output data.

As described above, the bit synchronization circuit 10 includes the delay circuit 11 for delaying the system clock by １ ／, ２, and ／ cycle, the phase comparison pulse generation circuit 12, and the phase selection circuits 13 and 14. , A phase comparison circuit 15, a phase determination circuit 16, and a latch circuit 17, a system clock is multi-phased by a delay circuit 11, and a pulse is generated at a change point of received data and a rising point of the multi-phase clock. A phase comparison is performed using the data, and a clock phase for data punching is controlled based on the comparison result.

FIG. 2 is a circuit diagram showing the configuration of the phase comparison circuit 15. In FIG. 2, a phase comparison circuit 15 includes a phase comparison circuit A18 composed of a flip-flop using a data transition point pulse as a data input and a clock rising pulse as a clock, and a phase transition circuit A18 with a clock rising pulse as a data input and a data transition point pulse as a data input. And a phase comparison circuit B19 comprising a flip-flop. The setup time determination result is output from the phase comparison circuit A18, and the hold time determination result is output from the phase comparison circuit B19.

The operation of the bit synchronization circuit 10 configured as described above will be described below.

First, the system clock is supplied to delay circuits 1 to 3
To the delay circuit 11 composed of The delay circuit 11 delays 1/4, 1/2, and 3/4 cycle of the system clock, respectively, to generate a 4-phase clock as shown in FIG.

The generated four-phase clock and the received data are input to the phase comparison pulse generation circuit 12, and the phase comparison pulse generation circuit 12 generates a pulse having a constant width at the rising edge of the clock and at a data change point. . This pulse is called a clock rising pulse. The pulse width is set to be equal to or longer than the setup / hold time at the time of final latching.

The generated clock rising pulse is input to the phase selection circuit 13, the phase of which is selected by the phase selection circuit 13, and then input to the phase comparison circuit 15.

In the phase comparison circuit 15, the phase comparison is performed by the circuit shown in FIG. The phase comparison is performed by using a pulse generated at a change point of received data (hereinafter referred to as a data change point pulse) with a clock rising pulse having a selected phase (hereinafter referred to as phase comparison A) and a clock rising pulse as described above. What is punched by a change point pulse (hereinafter referred to as phase comparison B) is used.

The phase comparison A is for judging the setup time of the selected clock and data. When the data change point pulse is missed by the clock rising pulse,
It is determined that the setup time may not be satisfied.

Similarly, the phase comparison B is for judging the hold time of the selected clock and data. If the clock rising pulse is missed by the data change point pulse, the hold time may not be satisfied. to decide.

The phase determination circuit 16 uses an UP / DOWN counter. When it is determined that the setup time may not be satisfied as a result of the phase comparison A for the currently selected clock phase, the selected clock is selected. Control to increase the setup time by delaying the phase.

Conversely, if it is determined from the phase comparison B that there is a possibility that the hold time may not be satisfied, control is performed to increase the hold time by advancing the phase of the selected clock. This control is performed by transmitting the phase selection signal to the phase selection circuit 1.
This is performed by outputting to the third and the fourth.

If it is determined that both the setup and hold times are satisfied as a result of the phase comparisons A and B, the currently selected phase is held.

The phase selection circuit 14 includes a phase determination circuit 16
The clock phase is selected according to the result of the determination. The latch circuit 17 uses the clock selected by the phase selection circuit 14 to latch the received data.

As described above, the bit synchronization circuit 10 according to the first embodiment includes a delay circuit 11 for delaying a system clock, a phase comparison pulse generation circuit 12, phase selection circuits 13 and 14, and a phase comparison circuit 15 , A control means 50 including a phase determination circuit 16 and a latch circuit 17,
The system clock is multi-phased by the delay circuit 11, the phase comparison pulse generation circuit 12 generates a pulse at the change point of the received data and the rising point of the multi-phase clock, and performs phase comparison using the pulse generated by the control means 50. Since the clock phase for data punching is controlled based on the comparison result, the clock is delayed and multi-phased, so that bit synchronization can be achieved without using a high-speed clock exceeding the received data. .

Further, in the case of four-phase clock, up to two phase changes are required until the optimum phase is selected at the time of phase selection, and high-speed bit synchronization can be performed, so that burst signals can be handled. Further, when the clock phase is changed, the setup time or the hold time is changed in a direction of increasing the data, so that double hitting of data is prevented, and accurate data reproduction is enabled.

FIG. 4 is a circuit diagram showing a configuration of a bit synchronization circuit according to a second embodiment of the present invention, and shows a configuration example of a bit synchronization circuit when data is multi-phased. Here, an example in which four phases are formed as in the first embodiment will be described. Note that, in describing the bit synchronization circuit according to the present embodiment, FIG.
The same components as those of the bit synchronization circuit shown in FIG.

In the first embodiment, the clock is multi-phased by delay, but in this embodiment, the received data is multi-phased by inputting the received data to the delay circuit. This bit synchronization circuit is configured by adding a reset signal to the bit synchronization circuit described in the first embodiment.

In FIG. 4, a bit synchronization circuit 20 includes a delay circuit 11 for delaying received data by three delay circuits 1 to 3 having different delay times, a phase comparison pulse generation circuit 12, and two phase selection circuits 13 , 14 (phase selection circuits 1 and 2), phase comparison circuit 15, phase determination circuit 16,
It comprises a latch circuit 17.

The received data, system clock and reset signal are used as inputs. The reset signal resets the phase selection circuits 13 and 14 between the burst signals.
By receiving the reset signal, the phase selection circuits 13 and 14 select the intermediate phase of the selected data from among the multi-phase data phases.

The received data is input to the delay circuit 11, and each of the received data is １ ／ of the system clock, 1
/ 2, 3/4 period delay.

The generated four-phase data is supplied to the phase selection circuit 1
4 and the phase comparison pulse generation circuit 12. The phase comparison pulse generation circuit 12 also receives a system clock. The four-phase data change point pulse pulsed by the phase comparison pulse generation circuit 12 is
In step 3, one is selected and input to the phase comparison circuit 15 together with the clock rising pulse, and the phase comparison circuit 15 performs phase comparison.

The comparison result is input to the phase determination circuit 16, and the determination result by the phase determination circuit 16 is input to the phase selection circuits 13 and 14 as a phase selection signal.

The phase selection circuit 14 selects one of the input four-phase data and outputs it as latch data. The latch circuit 17 latches and outputs the output data from the phase selection circuit 14 using the system clock.

Hereinafter, the operation of the bit synchronization circuit 20 configured as described above will be described.

In the delay circuit 11, the system clock 1
/ 4, 1/2, and 3/4 cycles are delayed to generate four-phase data as shown in FIG.

The four-phase data and the system clock are input to the pulse generation circuit 12 for phase comparison. The phase comparison pulse generation circuit 12 generates a pulse having a constant width at the rising edge of the clock and at the data change point. The pulse width is set to be equal to or longer than the setup / hold time at the time of final latching.

The generated data change point pulse is input to the phase selection circuit 13, and after the phase selection circuit 13 selects the phase,
It is input to the phase comparison circuit 15.

In the phase comparison circuit 15, the phase comparison is performed by the circuit shown in FIG. In the phase comparison, as in the first embodiment, a selected data change point pulse is punched out by a clock rising pulse (phase comparison A), and a clock rising pulse is punched out by a selected data change point pulse ( Use phase comparison B).

The phase comparison A is for judging the setup time of the system clock and the data of the selected phase. If the data transition point pulse is missed by the rising edge of the clock, the setup time may not be satisfied. I do.

Similarly, the phase comparison B determines the hold time of the system clock and the data of the selected phase. If the clock rising pulse is missed by the data change point pulse, the hold time may not be satisfied. Occurs.

The UP / DOWN counter is used for the phase determination circuit 16. When the setup time is not satisfied as a result of the phase comparison A with the currently selected data phase, the phase of the selected data is advanced. Control to increase the setup time.

Conversely, if it is determined that the hold time is not satisfied as a result of the phase comparison B, the control of increasing the hold time is performed by delaying the phase of the selected data.

If it is determined that the comparison results of the phase comparisons A and B both satisfy the setup / hold time, the currently selected phase is held.

The phase selection circuit 14 includes a phase determination circuit 16
The data phase is selected according to the result of the determination. The latch circuit 17 uses the data selected by the phase selection circuit 14 and latches the data with a system clock.

As described above, the bit synchronization circuit 20 according to the second embodiment reduces the system clock by 1/4,
Delay circuit 11 for delaying by 、 ３, ／ cycle, phase comparison pulse generation circuit 12, phase selection circuits 13 and 14, phase comparison circuit 15, phase determination circuit 16, and latch circuit 17
Control means 50 comprising a delay circuit 1
1, the phase comparison pulse generation circuit 12 generates a pulse at the transition point of the received data and at the rising point of the multiphase clock, and performs a phase comparison using the pulse generated by the control means 50. Since the clock phase for data punching is controlled, the data can be delayed and multi-phased, so that bit synchronization can be achieved without using a higher-speed clock than received data.

Further, by inputting a reset signal between burst signals, a maximum of two phase changes are required in the case of data four-phase until an optimum phase is selected at the time of phase selection. Therefore, it can respond to a burst signal.

When the phase of the data is changed, the setup time or the hold time is changed so as to increase, so that the data is prevented from being hit twice and accurate data reproduction is enabled. Further, even when the phase is changed as a result of the phase determination, control can be performed without changing the phase of the clock.

Therefore, the bit synchronization circuit having such excellent features is suitably applied to a PDS system for transmitting a burst signal.

FIG. 6 shows the bit synchronization circuit 10 shown in FIG.
Is applied to a PDS system.

This system is composed of a device (station device 100) installed on the PDS system station side and a device (subscriber device 200) installed on the subscriber side. The optical line terminal 100 is connected to a plurality of optical line units 200 using an optical fiber via a star coupler (SC) 300.

When data is transmitted from the optical line terminal 100 to the subscriber unit 200, the data is transmitted continuously, and the subscriber identifies the transmission destination of the data and receives the data. When transmitting data from the device 200 to the optical line terminal 100, since the plurality of subscriber devices transmit data at the respective permitted timings, the optical line terminal 100 receives the received data as a burst signal.

When this bit synchronization circuit is used for the data receiving circuit of the optical line terminal 100, high-speed synchronization is possible, so that bit synchronization can be realized in a small preamble section, and transmission efficiency can be improved.

The same effect can be obtained when the bit synchronization circuit 20 of FIG. 4 is used in the optical line terminal 100.

In each of the above embodiments, the bit synchronization circuits 10 and 20 can be applied to the bit synchronization circuit corresponding to the burst transmission in the high-speed PDS system described above. Further, the present invention can be applied to all devices that receive binary digital signals, not limited to burst signals.

It is needless to say that the type / number of delay circuits, selection circuits, comparison circuits, etc. constituting the bit synchronization circuit, the number of polyphases, and the like are not limited to the above-described embodiment.

[0073]

The bit synchronization circuit according to the present invention is a bit synchronization circuit for changing the received data to the system clock, the delay means for delaying the system clock to multi-phase, the change point of the received data and the delay. Means for generating a pulse at the rising point of the polyphase clock multiplied by the means, and phase comparison using the pulse generated by the pulse generation means, and controlling the clock phase for data punching based on the comparison result. With control means, it is compatible with burst signals, synchronizes at high speed, has good tracking characteristics to phase fluctuations of continuous signals, and accurately receives received data without using a high-speed clock. Data can be reproduced.

In the bit synchronization circuit according to the present invention, there is provided a bit synchronization circuit for changing received data to a system clock, and a delay means for delaying received data to make it multi-phase.
A phase comparison is performed using a pulse generation means for generating a pulse at a change point of the system clock and a rising point of the polyphase data multi-phased by the delay means, and a phase comparison is performed using the pulse generated by the pulse generation means. And a control means for controlling the data phase for data transmission.By adding a reset signal between burst signals, it is possible to cope with burst signals, perform high-speed synchronization, and provide good control over phase fluctuations of continuous signals. It has a tracking characteristic and can accurately reproduce data without using a high-speed clock for received data.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a bit synchronization circuit according to a first embodiment to which the present invention has been applied.

FIG. 2 is a circuit diagram showing a configuration of a phase comparison circuit of the bit synchronization circuit.

FIG. 3 is a waveform diagram showing multi-phase of a clock using a delay circuit of the bit synchronization circuit.

FIG. 4 is a circuit diagram showing a configuration of a bit synchronization circuit according to a second embodiment to which the present invention has been applied.

FIG. 5 is a waveform diagram showing multi-phase data using a delay circuit of the bit synchronization circuit.

FIG. 6 is a diagram illustrating an application example of a PDS system of the bit synchronization circuit.

[Description of Signs] 10, 20-bit synchronization circuit, 11 delay circuit (delay means), 12 phase comparison pulse generation circuit (pulse generation means), 13, 14 phase selection circuit (phase selection circuit 1,
2), 15 phase comparison circuit, 16 phase determination circuit, 17
Latch circuit, 50 control means

Claims (6)

[Claims] 1. A bit synchronization circuit for changing received data to a system clock, a delay means for delaying the system clock to make it multi-phase, a change point of the received data and a multi-phase being made by the delay means. Pulse generating means for generating a pulse at a rising point of the multi-phase clock, and control means for performing a phase comparison using the pulse generated by the pulse generating means and controlling a clock phase for data punching based on the comparison result. A bit synchronization circuit. 2. A bit synchronization circuit for changing received data to a system clock, wherein the delay means delays the received data to form a multi-phase, and the multi-phase is formed by a change point of the system clock and the delay means. Pulse generating means for generating a pulse at the rising point of the polyphase data, and control means for performing a phase comparison using the pulse generated by the pulse generating means, and controlling a data phase for data punching based on the comparison result. A bit synchronization circuit. 3. The phase comparison by the control means includes: a phase comparison A in which a data change point pulse generated at a change point of the received data is punched out with a clock rising pulse having a selected phase; 3. The bit synchronization circuit according to claim 1, wherein a phase comparison B punched by a point pulse is used. 4. The control means determines that the setup time may not be satisfied if the phase comparison A misses the data transition point pulse with the clock rising pulse. 4. The bit synchronization circuit according to claim 3, wherein if B misses the clock rising pulse with the data transition point pulse, it determines that the hold time may not be satisfied. 5. The control means, when determining that there is a possibility that the setup time may not be satisfied with respect to the currently selected clock phase based on the result of the phase comparison A, changes the phase of the selected clock. In addition to performing the control to increase the setup time by delaying, if it is determined that the hold time may not be satisfied based on the result of the phase comparison B, the control to increase the hold time by advancing the phase of the selected clock And based on the results of the phase comparison A and the phase comparison B,
5. The bit synchronization circuit according to claim 3, wherein when it is determined that both the setup and hold times are satisfied, control is performed so as to maintain the currently selected phase. 6. The controller according to claim 1, wherein the controller compares the phase comparison A with a currently selected data phase.
If it is determined that there is a possibility that the setup time may not be satisfied based on the result of the above, while performing control to increase the setup time by delaying the phase of the selected data, based on the result of the phase comparison B, If it is determined that there is a possibility that is not satisfied, by performing the control of increasing the hold time by advancing the phase of the selected clock, based on the results of the phase comparison A and the phase comparison B,
5. The bit synchronization circuit according to claim 3, wherein when it is determined that both the setup and hold times are satisfied, control is performed so as to maintain the currently selected phase.