JPH0964858A - Phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a stable extract circuit by providing a polyphase clock generating means and selecting a data latch means corresponding to a phase of a clock whose change point is detected by the clock phase detection means among data latch means. SOLUTION: Each of data latch circuits 9, 9,... latches burst data corresponding to a phase of each clock generated by a polyphase clock generating circuit 3. A clock selection circuit 4, a clock decision circuit 5, and a decision result latch circuit 6 select and decide a desired clock phase from each clock signal generated by the circuit 3 based on a change point of the burst data detected by a change point detection circuit 2. Then output data from the data latch circuit 9 corresponding to the phase of the clock to be decided are selected as output object data by a data selector 10. That is, when the selection of the clock signal is decided by the selector 10, the phase of the clock is unchanged.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the field of phase locked loop circuits in digital data transmission.

[0002]

2. Description of the Related Art Conventionally, for example, as shown in FIG. 2, in a system such as a point / multipoint transmission system in which a plurality of slave devices are connected to a main device, data having different phases must be used. A phase locked loop is used. FIG. 2 is a schematic diagram showing an example of a system configuration based on the point / multipoint transmission method. That is, in the point / multipoint transmission system as shown in FIG. 2, since the connection distance between the main device and each slave device is generally different, the transmission data from each slave device received by the master device side The phases are also different.

In order for the main unit to correctly receive such data having different phases, the phase synchronization circuit transmits each transmission data transmitted in a form in which a bit for phase synchronization extraction is added to the transmission data from the slave unit. It is for synchronization. However, adding a bit for phase synchronization extraction in order to synchronize the transmission data means that the amount of data that can be transmitted within a certain period of time decreases, and in order to transmit a predetermined amount of data, the transmission rate must be increased. It is necessary to raise it. Therefore, it has been conventionally considered to make the bit for phase synchronization extraction as short as possible.

The phase synchronization circuit is, for example, PL
It is generally known that the L (Phase Locked Loop) method, the multipoint sampling method, and the polyphase selection method are used. When these methods are applied to the above point / multipoint transmission method, the PLL method uses It has been pointed out that the multi-point sampling method requires a clock signal that is several times faster than the transmission speed, and that the multi-phase selection method is effective for the point / multi-point transmission method. It has become more common than before.

FIG. 3 is a block diagram showing an example of a phase locked loop using the conventional multi-phase selection method, and FIG. 4 is a timing chart showing the output waveform from each circuit in the phase locked loop of FIG. is there. In FIG. 3, the phase synchronization circuit 1
Includes a change point detection circuit 2, a multiphase clock generation circuit 3, a clock selection circuit 4, a clock determination circuit 5, a determination result holding circuit 6, a multiphase clock selector 7, and a data reproduction circuit 8.

The change point detection circuit 2 detects a change point (clock rising point and clock falling point) of the received burst data. The multi-phase clock generation circuit 3 generates a multi-phase clock signal by shifting a reference clock signal (hereinafter referred to as a reference clock signal) for a predetermined time. In this example, the reference clock signal is included. Generate clock signals for four phases.

At the rising timing of the output pulse from the clock selection circuit 4 and the change point detection circuit 2, the output clock signal of the multi-phase clock generation circuit 3 is latched to determine which phase of the multi-phase clock has the change point. It is for finding. The clock determination circuit 5 is a circuit for protecting the clock selection circuit 4, and when a predetermined condition is satisfied (in this case, when there is a change point in the same phase twice in a row), a clock phase that satisfies the condition is determined. To do.

The decision result holding circuit 6 is a circuit for holding the clock phase decided by the clock decision circuit 5, and the multiphase clock selector 7 selects from among the clock signals generated by the multiphase clock generation circuit 3. , A circuit for selecting only the phase held by the decision result holding circuit 6. The data reproduction circuit 8 is a circuit for matching the data phase with the clock signal selected by the multi-phase clock selector 7.

In the above-mentioned configuration, with respect to the change point of the input burst data, the clock phase is determined from the clock signals of four phases, the clock signal of the clock phase is selected, and the selected clock is selected. Phase synchronization is established by matching the data phase to the signal.

[0010]

However, in such a conventional phase locked loop circuit 1 as described above, since the multiphase clock signal is selected by the multiphase clock selector 7, the following will be described. There was a problem. That is, when the clock signal selection is determined by the multi-phase clock selector 7, the clock phase changes, so the clock phase of the selector output must be shifted or the clock signal must not be output until the clock phase is determined. In order to guarantee stable operation in the subsequent circuit, a bit for phase synchronization extraction longer than the clock decision logic is needed.

Further, if the bit length for phase synchronization extraction is made long, stable clock phase selection becomes possible, but it is required to further increase the transmission speed, and if the bit length is made short, clock phase selection becomes possible. There was a problem that it became difficult. As described above, even when the multi-phase selection method is used, the minimum number of bits for phase synchronization extraction is required, and the addition of these bits for phase synchronization extraction inevitably increases the transmission rate.

An object of the present invention is to solve the above problems and to provide a phase synchronization circuit which can establish stable phase synchronization without adding a phase synchronization extraction bit.

[0013]

According to the phase locked loop circuit of the present invention, in a phase locked loop circuit for establishing synchronization in digital data transmission, a multi phase clock generation means for generating a multi phase clock signal based on a reference clock signal. And a clock phase detection for latching an output clock signal generated by the multi-phase clock generation means based on a change point of transmitted burst data and detecting which phase of the output clock signal has a change point. Means, a plurality of data holding means for respectively holding the transmitted burst data corresponding to the clock phases generated by the multi-phase clock generating means, and a clock phase detecting means from among the plurality of data holding means. The data held in the data holding means is selected by selecting the data holding means corresponding to the clock phase where the change point is detected. It is configured with a data selection means to output data.

In this case, as described in claim 2, the clock phase detecting means includes a change point detecting section for detecting a change point of the transmitted burst data, and a change point detected by the change point detecting circuit. And a clock selection unit that latches the output clock signal generated by the multi-phase clock generation means and detects in which phase the clock change point exists,
When the clock phase detected by the clock selection unit has continuous change points, a clock determination unit that determines the clock phase as a target clock phase, and a result that holds the clock phase determined by the clock determination unit It is preferable to have a holding part.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the phase locked loop circuit in the present embodiment. FIG.
In FIG. 3, the same elements as those of the conventional example shown in FIG. The phase-locked loop circuit 1 of the present embodiment is roughly classified into a multi-phase clock generation circuit 3 serving as multi-phase clock generation means, a change point detection circuit (change point detection section) 2 having a function of clock phase detection means 2, and clock selection. Circuit (clock selection unit) 4, clock determination circuit (clock determination unit) 5,
A decision result holding circuit (result holding unit) 6, a plurality of data holding circuits 9, 9, ... As data holding means, and a data selector 10 as data selecting means.

The data holding circuits 9, 9, ... Are circuits for storing burst data for each phase of the clock signal generated by the multi-phase clock generation circuit 3. For example, the data holding circuits 9, 9 ,. When the clock signals for four phases including the clock signal are generated, the data of each phase is stored by the four data holding circuits 9, 9, ... Corresponding to each phase. The data selector outputs the data clock signal corresponding to the clock phase held by the decision result holding circuit 6 to the data holding circuit 9,
It is a circuit to be selected from 9, ...

Next, the operation of the above embodiment will be described. First, each data holding circuit 9, 9, ... Corresponding to each clock phase generated by the multi-phase clock generation circuit 2.
Burst data is held in. Then, based on the change point (clock rising point or falling point) of the burst data detected by the change point detection circuit 3, the clock selection circuit 4, the clock determination circuit 5, and the decision result holding circuit 6 generate a multi-phase clock. A desired clock phase is selected / determined from each clock signal generated by the circuit 2. Next, the output data from the data holding circuit 9 corresponding to the determined clock phase is selected as the output target data by the data selector 10.

That is, in the present embodiment, the clock phase does not change when the data selector 10 determines the clock signal selection.
It is not necessary to shift the clock phase of the selector output or prevent the clock signal from being output until the clock phase is determined. Therefore, in order to guarantee a stable operation in the subsequent circuit, it is not necessary to use the bit for phase synchronization extraction.

In the above-described embodiment, the multi-phase clock signal generated in the multi-phase clock generation circuit 3 includes four phases including the reference clock signal, but the number of phases can be set arbitrarily. is there. Further, the clock decision circuit 5 decides the clock phase when there is a change point in the same phase twice consecutively in order to protect the clock selection circuit 4, but the decision conditions are various conditions. Needless to say, it can be changed according to.

[0020]

According to the present invention, in the point / multipoint transmission system, it is possible to realize a stable phase synchronization clock extraction circuit without transmitting bits for phase synchronization extraction, and add bits for phase synchronization extraction. By doing so, it is possible to avoid an increase in transmission speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a phase locked loop circuit according to an embodiment.

FIG. 2 is a schematic diagram showing an example of a system configuration based on a point / multipoint transmission system.

FIG. 3 is a block diagram showing an example of a phase synchronization circuit using a conventional polyphase selection method.

4 is a timing chart showing output waveforms from each circuit in the phase locked loop circuit of FIG.

[Explanation of symbols]

 1 phase synchronization circuit 2 change point detection circuit (change point detection unit) 3 multi-phase clock generation circuit (multi-phase clock generation means) 4 clock selection circuit (clock selection unit) 5 clock determination circuit (clock determination unit) 6 hold decision result Circuit (result holding unit) 7 Multi-phase clock selector 8 Data recovery circuit 9 Data holding circuit (data holding means) 10 Data selector (data selection means)

Claims (2)

[Claims] 1. A phase locked loop circuit for establishing synchronization in digital data transmission, which comprises: a multi-phase clock generation means for generating a multi-phase clock signal based on a reference clock signal; and a multi-phase clock generation means. The output clock signal is latched on the basis of the change point of the transmitted burst data, and the clock phase detecting means for detecting which phase of the output clock signal has the change point, and the transmitted burst data are A plurality of data holding means respectively holding the clock phases generated by the phase clock generating means, and data corresponding to the clock phase of which the change point is detected by the clock phase detecting means from among the plurality of data holding means A data selecting means for selecting a holding means and outputting the data held in the data holding means as output data; Phase locked loop, characterized in that it comprises. 2. The clock phase detecting means includes a change point detecting section for detecting a change point of transmitted burst data, and a change point detected by the change point detecting circuit generated by the multi-phase clock generating means. A clock selection unit that latches the output clock signal and detects the clock change point in which phase, and if there is a continuous change point in the clock phase detected by the clock selection unit, The phase synchronization circuit according to claim 1, further comprising: a clock determination unit that determines a target clock phase, and a result retaining unit that retains the clock phase determined by the clock determination unit.