JP3047532B2 - Separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demultiplexer for a multiplex converter for receiving a multiplexed signal through two or more transmission lines.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a demultiplexing circuit of a multiplex converter of this kind has at least two transmission lines a and b.
Has a receiving unit 1 corresponding to. Each receiving unit 1
Has a receiver circuit 2 for outputting a reception multiplexed signal a1.
A frame synchronization circuit 3 for detecting and outputting a reception multiplexing frame phase a2 from the reception multiplexing signal a1, and adjusting the reception multiplexing frame phase a1 to an in-device multiplexing frame phase c from the control circuit 9. And a frame aligner circuit 8 for outputting the intra-device multiplexed signal a3.

The multiplexed signals a3 and b3 output from the receiving units 1 are supplied to a TSI circuit 10. This T
In the SI circuit 10, the corresponding channel is separated by the control of the control circuit 9 which manages and controls the inside of the device in a unified manner, and the separated channel is supplied to each channel unit 4.

Next, the operation of the above-described conventional separation circuit will be described with reference to a time chart example of the frame aligner circuit 8 shown in FIG.

In this example, it is assumed that an N-channel multiplexed signal is received by a receiver 1 via a transmission line a, and a receiver multiplexed signal a1 is output from a receiver circuit 2. The frame synchronization circuit 3 establishes reception multiplexing frame synchronization from the reception multiplexing signal a1 and supplies the reception multiplexing frame phase a2 to the frame aligner circuit 8.

The frame aligner circuit 8 adjusts the frame phase of the received multiplexed signal a1 to the multiplexed frame phase c output from the control circuit 9 and outputs the multiplexed signal a3 to the TSI circuit 10. . The same operation as described above is performed on the received multiplexed signal received via the transmission line b, and the multiplexed signal b3
Is output from the other receiver 1 to the TSI circuit 10.

The TSI circuit 10 is controlled by the control circuit 8 which performs centralized control because the phases of the input multiplexed signals a3 and b3 are locked to the multiplexed frame phase c. The specified corresponding channel is separated and supplied to each channel unit 4.

However, in the conventional separation circuit, since the frame aligner circuit 8 adjusts the phase to the multiplexed frame phase c in the device, the received multiplexed signal a1 is at most one multiplexed signal. Delayed by a period,
There is a problem that the delay time increases.

An object of the present invention is to provide a separation circuit having a relatively small delay time.

[0009]

In order to achieve this object, a demultiplexing circuit according to the present invention is provided corresponding to at least two transmission paths for transmitting a multiplexed signal and each transmission path. A receiving unit for receiving the multiplexed signal; and a channel unit provided corresponding to each channel and supplied with the received multiplexed signal and the channel pulse output from each of the receiving units. A receiver circuit for performing interface conversion of the received multiplexed signal and outputting a received multiplexed signal, and a frame synchronization circuit for establishing frame synchronization of the received multiplexed signal and outputting a received multiplexed frame phase. A reception pulse generation circuit that generates a channel pulse of each channel of the reception multiplexed signal according to the reception multiplexing frame phase,
The channel section includes a selection circuit for selecting and outputting a designated reception multiplexed signal and a designated channel pulse, and a channel for the reception multiplexed signal selected by the selection circuit. And a channel circuit separated by the

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a separation circuit according to the present invention.

FIG. 1 shows the configuration of the embodiment. In addition,
In FIG. 1, components corresponding to those shown in FIG. 2 are denoted by the same reference numerals.

In FIG. 1, receiving sections 1 and 1 for receiving one multiplexed signal are provided corresponding to at least two transmission paths a and b through which the multiplexed signal is transmitted.
Each of the receiving units 1 and 1 performs interface conversion of the received multiplexed signal and outputs a received multiplexed signal a1 (b1), and establishes frame synchronization of the received multiplexed signal a1 and performs reception multiplexing. Frame phase a2 (b
2) and the received multiplexed signal a1 (b) based on the received multiplexed frame phase a2 (b2).
1) a reception pulse generation circuit 6 for generating a channel pulse of each channel.

The received multiplexed signal a1 (b1) and the channel pulse output from each of the receiving units 1 and 1 are supplied to a channel unit 4. The channel unit 4 includes a selection circuit 5 for selecting and outputting the reception multiplexed signal a1 (b1) and the channel pulse supplied from the designated reception unit 1 among the reception units 1, The reception multiplexed signal a1 (b1) selected by the circuit 5 has a channel circuit 7 for separating a specified channel by the selected channel pulse.

Next, the operation in this configuration will be described.

The received multiplexed signal supplied through the transmission line a is subjected to interface conversion in the receiver circuit 2 of the receiving unit 1 and converted into a received multiplexed signal a1 to be transmitted to the frame synchronization circuit 3 and each channel unit 4. Supplied. The frame synchronization circuit 3 establishes frame synchronization of the reception multiplex signal a1 and supplies the reception multiplex frame phase a2 to the reception pulse generation circuit 6.

The reception pulse generation circuit 6 creates a channel pulse of the reception multiplexed signal a1 of the reception unit 1 based on the supplied reception multiplexing frame phase a2 and sends it to each channel unit 4.

The reception multiplexed signal supplied through the transmission path b and another transmission path (not shown) is also processed by the reception unit 1 in the same manner.

Next, in the channel unit 4, the selection circuit 5 selects the received multiplexed signal a1 and the like and the channel pulse from the received multiplexed signal of the receiver 1 specified by the mounting slot and the channel pulse. And outputs it to the channel circuit 7.

The channel circuit 7 separates a designated channel from the received multiplexed signal according to the selected channel pulse.

The other channel units 4 operate in the same manner to form a separation circuit for all the received multiplexed signals.

As for the channel selection designation of the selection circuit 5 in the channel section 4, the means for realizing the designation of the mounting slot, the designation of the package, the designation of the batch management, etc., including the method of assigning the total channel number for the whole device, are prescribed. That is not done.

[0022]

As is apparent from the above description, the demultiplexing circuit of the present invention generates channel pulses corresponding to the respective received multiplexed frame phases, and the channel section receives the multiplexed signal based on the channel pulses. The channels are separated. For this reason, it is not necessary to use the frame aligner circuit as described in the section of the related art, and the effect that the delay time of the separation circuit is relatively reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a separation circuit of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a separation circuit according to a conventional technique.

FIG. 3 is a time chart for explaining the operation of the conventional separation circuit shown in FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving part 2 Receiver circuit 3 Frame synchronizing circuit 4 Channel part 5 Selection circuit 6 Reception pulse generation circuit 7 Channel circuit a, b Transmission line a1, b1 Reception multiplexed signal a2, b2 Reception multiplexing frame phase a3, b3 In-device multiplexing Signal

Claims (1)

(57) [Claims] At least two transmission paths through which a multiplexed signal is transmitted, a reception section provided corresponding to each transmission path and receiving the multiplexed signal, and a reception section provided corresponding to each channel A channel unit to which a reception multiplexed signal and a channel pulse output from the respective reception units are supplied, wherein the reception units respectively perform interface conversion of the received multiplexed signal and perform a reception multiplexed signal. And a frame synchronization circuit that establishes frame synchronization of the reception multiplexed signal and outputs a reception multiplexed frame phase, and a channel pulse of each channel of the reception multiplexed signal based on the reception multiplexed frame phase. And a reception pulse generation circuit for generating a reception multiplexed signal and a designated reception multiplexed signal. A separation circuit, comprising: a selection circuit that selects and outputs a channel pulse; and a channel circuit that separates a channel of the reception multiplex signal selected by the selection circuit by the selected channel pulse.