JPS62175022A - Signal transmission system using mbnb converting code as transmission line code - Google Patents

Signal transmission system using mbnb converting code as transmission line code

Info

Publication number
JPS62175022A
JPS62175022A JP61015729A JP1572986A JPS62175022A JP S62175022 A JPS62175022 A JP S62175022A JP 61015729 A JP61015729 A JP 61015729A JP 1572986 A JP1572986 A JP 1572986A JP S62175022 A JPS62175022 A JP S62175022A
Authority
JP
Japan
Prior art keywords
code
frame
transmission line
signal
mbnb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61015729A
Other languages
Japanese (ja)
Inventor
Masanori Miura
正範 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61015729A priority Critical patent/JPS62175022A/en
Publication of JPS62175022A publication Critical patent/JPS62175022A/en
Pending legal-status Critical Current

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  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To decrease the number of a memories by inserting a dispersion type synchronizing pattern and an auxiliary data signal in (n) bit unit as a frame constitution. CONSTITUTION:In a signal transmission system to use a mBnB converting code as a transmission line code, the transmission line has a frame synchronizing pattern and an auxiliary data signal at the equal interval in (n) bit unit in one frame. One frame length 1 is the multiple of 6 and a synchronizing frame pattern 2 is dispersed and arranged by a 6-bit unit. An auxiliary data signal 3 is dispersed and arranged in 6-bit unit, and an information signal 4 is a signal applied with 5B6B code conversion. When the frame constitution is used as a transmission line code, the toothless clock output of a thinned pulse generating part 23 comes to be a 1-bit thinned clock, and when a transmission line jitter, etc., are considered, four bits are sufficient in the number of the memory of a memory part 16.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、伝送方式、特にそれに周込られる。[Detailed description of the invention] [Industrial application field] The invention relates to transmission systems, and more particularly to transmission systems.

ｍＢｎｎ符号変換によるフレーム構成に関する。This relates to a frame structure based on mBnn code conversion.

〔従来の技術〕[Conventional technology]

従来、この種のｍＢｎＢ符号変換を用いたフレーム構成
としては二通りある。第２図は例えば５Ｂ６Ｂを用いた
場合を示している。第２図において、（ａ）は、フレー
ム同期・ぐターンとして１２ビツトの集中型フレーム同
期パターン、補助ビットとして１２ビツトの補対ビット
を用いている。また第２図において、　（ｂ）は、同期
パターンとして２ビ、トの分散型フレーム同期・ぐター
ン、補助ビットとして２ビ、トを用いている。Conventionally, there are two types of frame configurations using this type of mBnB code conversion. FIG. 2 shows a case where, for example, 5B6B is used. In FIG. 2, (a) uses a 12-bit lumped frame synchronization pattern as a frame synchronization pattern and a 12-bit complementary bit as an auxiliary bit. Further, in FIG. 2, (b) uses a distributed frame synchronization pattern of 2 bits and 2 bits as a synchronization pattern and 2 bits of 2 bits as an auxiliary bit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のフレーム構成を伝送路符号として用いて
伝送する場合には、第３図のような回路構成を必要とす
る。When transmitting using the conventional frame structure described above as a transmission path code, a circuit structure as shown in FIG. 3 is required.

第３図の回路構成を簡単に説明する。先ず、ｆＷ報ビッ
ト４にて表わされたデータを直列−並列変換部１５によ
り５系列に分離し、エラスティックメモ９部１６に入れ
る。メモリ部１６からはフレーム同期・母ターン、補助
データ信号部分を除いた歯抜けのクロ、りでデータを読
み出す。そのデータをｍＢｎＢ符号変換部１７にて５Ｂ
６Ｂ符号変換する。The circuit configuration of FIG. 3 will be briefly explained. First, the data represented by the fW report bit 4 is separated into 5 series by the serial-parallel converter 15, and is input into the elastic memo 9 section 16. Data is read out from the memory unit 16 with frame synchronization, main turn, and auxiliary data signal portions in a seamless manner. The data is converted into 5B by mBnB code converter 17.
6B code conversion.

更にフレーム同期・ぐターン、補助データ信号を挿入後
、並列−直列変換部１８にて並列−直列変換を行なう。Further, after inserting frame synchronization, turn, and auxiliary data signals, a parallel-to-serial conversion section 18 performs parallel-to-serial conversion.

なお１９ばＩｎ分周回路、２０はｎ分周回路、２１は位
相比較回路、２３は歯抜け・やルス発生部である。Note that 19 is an In frequency divider circuit, 20 is an N frequency divider circuit, 21 is a phase comparator circuit, and 23 is a missing/loose generating section.

しかしながら、第３図の回路構成によって第２図（ａ）
のフレーム構成を実現する場合には１伝送路ノツク等を
考慮すると、メモリ部１６のメモリ数は５ビット以上必
要となる欠点があった。又、フレーム構成第２図（ｂ）
を実現する場合には、フレームの不均衡の為回路構成が
複雑になる欠点があった。However, due to the circuit configuration shown in FIG.
In order to realize this frame structure, there is a drawback that the number of memories in the memory section 16 needs to be 5 bits or more, taking into consideration one transmission path notch, etc. Also, frame configuration Figure 2 (b)
When realizing this, there is a drawback that the circuit configuration becomes complicated due to frame imbalance.

Ｃ問題点を解決するだめの手段〕 本発明によれば、伝送路符号としてｍＢｎＢ変換符号を
用いた信号伝送方式において、上記伝送路符号は、１フ
レーム中にｎビット単位で等間隔にフレーム同期・やタ
ーン及び補助データ信号を有するものであることを特徴
とする信号伝送方式が得られる。[Means for Solving Problem C] According to the present invention, in a signal transmission system using an mBnB conversion code as a transmission path code, the transmission path code is synchronized at regular intervals in units of n bits within one frame. A signal transmission system is obtained which is characterized in that it has a turn signal and an auxiliary data signal.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例における５Ｂ６Ｂ変換符号を
用いたフレーム構成を示す。１は１フレーム長で、６０
倍数である。２は同期フレームパターンで、６ビツト単
位で同図に示すように分散して配置する。３は、補助デ
ータ信号で、６ビツト単位で同図に示すように分散して
配置する。４は情報信号で、　５８６Ｂ符号変換された
信号である。FIG. 1 shows a frame structure using a 5B6B conversion code in an embodiment of the present invention. 1 is one frame length, 60
It is a multiple. 2 is a synchronization frame pattern, which is distributed and arranged in units of 6 bits as shown in the figure. Reference numeral 3 denotes an auxiliary data signal, which is distributed in units of 6 bits as shown in the figure. 4 is an information signal, which is a signal converted to a 586B code.

上述のフレーム構成を伝送路符号として用いる場合には
、第３図の回路における歯抜はパルス発生部２３の歯抜
はクロック中力は一ビツトの歯抜る。したがって上述の
フレーム構成を用いる場合の第３図の回路中のメモリ数
は、従来のフレーム構成を用いる場合のメモリ数より減
らすことができた。When the above-mentioned frame structure is used as a transmission line code, the circuit shown in FIG. 3 has no teeth, and the pulse generator 23 has no teeth, and the clock center power has one bit. Therefore, the number of memories in the circuit of FIG. 3 when using the above-described frame configuration can be reduced compared to the number of memories when using the conventional frame configuration.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、フレーム構成としてｎビ
ット単位で分散型の同期・ぞターン及び補助データ信号
を挿入することによりメモリ数を減らす効果を奏する。As described above, the present invention has the effect of reducing the number of memories by inserting distributed synchronization/cross-turn and auxiliary data signals in units of n bits as a frame structure.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は１本発明の一実施例に用いられるフレーム構成
を示し、第２図は、従来のフレーム構成を示し、第３図
は、　ｍＢｎＢ符号変換を用いる時の回路構成例を示す
。 １・・・１フレーム長、２・・フレーム同＃’ター１３
・・・補助ビット、４・・・情報ピッ）、１５・・・直
列−並列変換部、１６・・・エラスティックメモリ部。 １７・・・ｍＢｎ　Ｂ符号変換部、１８・・・並列−直
列変換部。 １９・・・ｍ分周回路、２０・・・ｎ分周回路、２１・
・・位相比較回路、２２・・・電圧制御発振器、２３・
・・歯抜け・ぐルス発生部。 第１図 （ｂ） 第２図FIG. 1 shows a frame structure used in one embodiment of the present invention, FIG. 2 shows a conventional frame structure, and FIG. 3 shows an example of a circuit structure when mBnB code conversion is used. 1...1 frame length, 2...frame same #'ter 13
... Auxiliary bit, 4 ... Information bit), 15 ... Serial-parallel conversion section, 16 ... Elastic memory section. 17... mBn B code converter, 18... Parallel-serial converter. 19...m frequency dividing circuit, 20...n frequency dividing circuit, 21...
... Phase comparator circuit, 22 ... Voltage controlled oscillator, 23.
・Tooth loss/Grus occurrence area. Figure 1 (b) Figure 2

Claims (1)

【特許請求の範囲】[Claims] １）伝送路符号としてｍＢｎＢ変換符号を用いた信号伝
送方式において、上記伝送路符号は、１フレーム中にｎ
ビット単位で等間隔にフレーム同期パターン及び補助デ
ータ信号等を有するものであることを特徴とする信号伝
送方式。1) In a signal transmission system using an mBnB conversion code as a transmission path code, the transmission path code is n
A signal transmission method characterized by having a frame synchronization pattern, an auxiliary data signal, etc. at equal intervals in bit units.
JP61015729A 1986-01-29 1986-01-29 Signal transmission system using mbnb converting code as transmission line code Pending JPS62175022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61015729A JPS62175022A (en) 1986-01-29 1986-01-29 Signal transmission system using mbnb converting code as transmission line code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61015729A JPS62175022A (en) 1986-01-29 1986-01-29 Signal transmission system using mbnb converting code as transmission line code

Publications (1)

Publication Number Publication Date
JPS62175022A true JPS62175022A (en) 1987-07-31

Family

ID=11896851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61015729A Pending JPS62175022A (en) 1986-01-29 1986-01-29 Signal transmission system using mbnb converting code as transmission line code

Country Status (1)

Country Link
JP (1) JPS62175022A (en)

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