JPH0226164A - Synchronous multiplexing system - Google Patents

Abstract

PURPOSE:To cause the width of a control signal to be N-dividing clock width and to form the control signal with a self-circuit by defining the N-dividing clock of an N-dividing counter in a serial/parallel(S/P) circuit as the data of the N-dividing counter in a P/P circuit. CONSTITUTION:Cascade connection is executed to an FFF/F1, an F/F2 and an F/F3 in a 6-dividing counter circuit 5' of a P/S circuit 4. An OR circuit is a logical circuit to input a 6-dividing clock g'' from a 6-dividing counter circuit 2' in the an S/P circuit 1 and a 6-dividing clock (j), which is the output of an inverted Q from the FFF/F3, and the output of the circuit OR is supplied to a terminal D of the FFF/F1 as input data (k) of the FF. Namely, the output (k) of the circuit OR, which defines the clock (j) and clock g'' from the circuit 2' as the input, is defined as the input signal of the FFF/F1 and the 6-dividing counter circuit 5' is operated. Thus, the control signal can be realized by a low speed element without being constituted in another circuit and energy consumption can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronization method within a core communication device, and particularly relates to a synchronization method in a backbone communication device.
Parallel conversion circuit (hereinafter referred to as S/P circuit) and parallel
This invention relates to a synchronous multiplexing method for a serial conversion circuit (hereinafter referred to as a P/8 circuit).

[Conventional technology]

An example of a conventional synchronization method is shown in FIG. 3 and will be described.

Conventionally, this type of synchronization method, as shown in Fig. 3,
The main signal, which is the input signal a, is divided into N parallel signals by the 8/P circuit 1, and the N parallel signals C processed by the signal processing section 3 are divided into P/P circuits. In the circuit configuration in which the S78 circuit is included and the parallel signal becomes a serial signal and is output as the output signal d, the N frequency division counter circuit 5 in the P/S circuit 4 is connected to the N frequency division counter circuit 2 in the S/P circuit 1.
A synchronized control signal (reset pulse) e is inputted to maintain synchronization. Note that f indicates a manual clock, and g indicates N.
The divided clock and h indicate the output clock.

[Problem to be solved by the invention]

In the conventional synchronization method described above, since the N-divided counter circuit is reset, the reset pulse width of the reset pulse e is half the width of the input clock f, and the N-divided counter circuit 5 must operate at high speed. There are nine issues.

Also, from the N frequency division counter circuit 2ON frequency division clock g in the S/P circuit 1, a narrow pulse (narrowp Hatake 1s
e) must be sent to the P/S circuit 4, synchronized with the manual clock f, and input to the P/S 78 circuit.
Make sure that it is always synchronized in the P/S circuit 4,
A protection circuit that does not immediately follow up even if an error occurs is also required, which not only increases the circuit scale but also increases power consumption.

[Means to solve the problem]

The synchronous multiplexing system of the present invention is a synchronous system including an 8/P circuit having an N (N: integer) frequency division counter circuit and a P/8 circuit having an N frequency division counter circuit that is different from the above N frequency division counter circuit. In the control signal for synchronizing the P/8 circuit with the 8/P circuit, the N-divided clock of the N-divided counter circuit in the 8/P circuit is applied to the N-divided clock of the N-divided counter circuit in the P/B circuit. It is designed to be used by ORing it with the N-divided clock.

[Effect]

In the present invention, N of the N frequency division counter in the S/P circuit is
Frequency division clock f (as the data of the N frequency division counter in the P/S circuit, and using the N frequency division clock of the N frequency division counter circuit in the S/P circuit, the N frequency division counter circuit in the P/S circuit Synchronize the clocks and multiplex the signals.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronous multiplexing system according to the present invention.

In FIG. 1, the same reference numerals as in FIG.
1, the N-divided clock of the N-divided counter circuit 2 in the S/P circuit 1 is ORed with the N-divided clock of the N-divided counter circuit 5 in the P/S circuit 4, and used. It is configured as follows.

The operation of the embodiment shown in FIG. 1 will now be explained.

First, the input clock f is converted into N-divided clocks g and 1 by the N-divided counter circuit 2 in the S/P circuit 1, and converted into N parallel signals by the input signal ai8/P circuit 1. Next, after data processing of these N parallel signals C is performed in the signal processing section 3, the P/S 78 converts them into N parallel signals C.
The signal is input to the circuit, and is output as an output signal (serial signal) d by the N-divided clock of the N-divided counter circuit 5. Here, the N frequency division counter circuit 5 in the P78 circuit 4 is 8/
N frequency division counter circuit 2ON frequency division clock in P circuit 1 (
An N-divided clock is created using the control signal) as data.

Figure 2 is a block diagram showing an embodiment of a divide-by-6 frequency counter circuit, and shows an example of use in the case of N-6.

In FIG. 2, the same reference numerals as in FIG.
*g' is a clock divided by 6.

Then, F/F1°F in the 6 frequency division counter circuit 5'
/F 2 and F/F 3 are flip-flops connected in cascade, and OR is the 6-divided clock g# from the 6-frequency divider counter circuit 2' and the 6-divided clock jt- which is the Q output of the flip-flop F/F3. This OR circuit is operated manually, and the output of the OR circuit OR is configured to be supplied to the terminal of the flip-flop F/F1 as input data for a 7-lig flop.

DPI, DP go...DP- and DP,',
DP,'...DP,' are parallel signals.

The operation of the embodiment shown in FIG. 2 will now be explained.

The output of the divide-by-6 clock circuit 5' in the P/S circuit 4, that is, the divide-by-6 clock j which is the Q output of the flip-flop F/F3, and the divide-by-6 clock j from the divide-by-6 counter circuit 2' of the S/P circuit 1. 6 frequency divided clock g1t-human-powered logical sum circuit OR
The flip-flop input data created by this logical sum is given as the input signal of the t1 flip-flop F/F1.
A 6 frequency division counter circuit 5' is operated.

〔Effect of the invention〕

As explained above, in the present invention, the control signal is set to the N-divided clock of the N-divided clock in the 8/P circuit - the data of the N-divided counter in the P/B circuit. The control signal does not need to be configured with other circuits, can be realized with low-speed elements, does not require high packaging density, and has the effect of reducing power consumption. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the synchronous multiplexing method according to the present invention, FIG. 2 is a block diagram showing an embodiment of a divide-by-6 counter circuit, and FIG. 3 is a block diagram showing an example of the conventional synchronous method. It is. 1...S/P circuit (serial-parallel conversion circuit), 2...
...N frequency division counter circuit, 4...P/S circuit (parallel-serial conversion circuit), 5...N frequency division counter circuit, O
R...OR circuit, l...Ill control signal. Figure 1 Figure 3

Claims (1)

[Claims] In a synchronous method including a series-to-parallel conversion circuit having an N (N: integer) frequency division counter circuit, and a parallel-to-serial conversion circuit having the N frequency division counter circuit and another N frequency division counter circuit, the parallel to series A control signal for synchronizing a conversion circuit with the series-to-parallel conversion circuit is used to convert the N-divided clock of the N-divided counter circuit in the serial-to-parallel conversion circuit into the N-divided clock of the N-divided counter circuit in the parallel-to-serial conversion circuit. A synchronous multiplexing method characterized in that it is used by ORing with a divided clock.