JPS5931899B2 - Synchronous pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization pulse generation circuit that generates pulses synchronized with bits of a digital signal.

For example, when the digital output of an A/D converter is obtained by bit parallel-digit serial, and the clock pulse of the register is generated in synchronization with the digit serial in order to input the digital output data into an external register,
Generally, a synchronous pulse generating circuit as shown in FIG. 1 is used.

In FIG. 1, 1 to 4 are input terminals 1) to (B4) of timing signals indicating each digit in series of four digit digital outputs, for example.

As shown in FIG. 4, the timing chart of the timing signals (Dl) to (B4) is as shown in FIG.
A pulse is generated in synchronization with the first digit of (B4), and (B2
) signal is the middle digit, (B3) signal is the hundreds digit, (B4)
The signal generates pulses in synchronization with each tens digit.

In Figure 4, the first digit is "9", the middle digit is "7",
BCD where the hundreds digit represents "8" and the tens digit represents "2"
Signals (B1) to (B4) are shown as examples.

5 to 8 are one-shot multi-by-breaks operated by the timing signals (Dl) to (B4), and one-shot pulses (Sl) to ( B4)
occurs.

After passing through the OR circuit 9, these pulses (Sl) to (B4) are appropriately delayed in the delay circuit 10, and the digital data (B1
) to (B4) are used for clock pulses for each digit.

The present invention provides a synchronizing pulse generating circuit with a simple structure that does not use elements such as the one-shot multi-by-break.

An embodiment of the present invention will be described below based on the drawings.

The timing signals used in FIG. 2 are (Dl) and (B3) or (B2) and (B4), and the case where (Dl) and (B3) are used will be described below.

Reference numeral 11.12 is an input terminal for a timing signal (DI) (Da), into which the timing signal shown at (DI) (B3) in FIG. 4 is input.

13 is an exclusive OR circuit, and input (DI
) When the levels of (B3) are equal, it becomes LI+, and when the levels are different, it becomes n H91.

Therefore, as shown in FIG.
A series of serial signals becomes L I+ level during periods (B2) and (B4).

14 is a pulse generator, and the waveform of its output (a) is asynchronous to the digital output as shown in FIG. 3a.

15 is a shift register, and the exclusive
It receives the signal A from the OR circuit 13 and operates using the pulse signal a of the pulse generator 14 as a clock, and sequentially stores and shifts the states of the signal A.

A and B are output terminals for adjacent bits of the shift register 15, and the leading terminal A outputs a signal C having a waveform as shown in FIG. A signal d with a waveform as shown in Fig. 3 d delayed by 1 minute is output, and each exclusive signal is
It is input to the OR circuit 16.

The exclusive OR circuit 16 operates in the same manner as the exclusive OR circuit 13 described above, and outputs a lock pulse e as shown in FIG. 3e.

17 is another shift register for digital output data (B1) to (B4), which sequentially stores and shifts bit-parallel data (B1) to (B4) by clock pulse e, and is synchronized with clock pulse e. Bit parallel data (B'l) to CB'4) are output.

As can be seen from Fig. 3, the clock pulse e is generated during the period of each timing signal (D,) to (B4), and therefore it is applied to each bit of the digital output data (B1) to (B4). It's in sync.

As described above, according to the present invention, since an unstable element that is susceptible to noise such as a one-shot multi-by-break is not used,
It has the advantage of reliable operation and simple structure.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a waveform diagram of each part of Fig. 2, and Fig. 4 is a bit parallel-digit series digital signal. 2 is a timing chart for explaining. 11.12... Timing signal input terminal, 13
...Exclusive OR circuit, 14...
...Pulse generator, 15...Shift register, 16...Exclusive OR circuit (clock pulse generation means), a...Pulse signal, e... ...clock pulse.

Claims (1)

[Claims] A signal whose level alternately switches for each digit is created from the timing signal of a digital signal including a plurality of serial timing signals that display one digit, and this signal is used as an input to generate pulses of a pulse generator. A shift register for clocking a signal is provided, and a clock pulse generating means is provided for serially extracting clock pulses corresponding to one bit period of the shift register from signals corresponding to adjacent bits of the shift register for each digit, A synchronization pulse generation circuit characterized in that the clock pulse generated from the clock signal generation means is used as a synchronization pulse of the digital signal. 2. The synchronizing pulse generating circuit according to claim 1, wherein the clock signal generating means is constituted by an exclusive OR circuit which inputs signals corresponding to adjacent bits of a shift register.