JP3125651B2 - Rate generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rate generator, and more particularly, to a rate generator used in an IC tester or the like and capable of setting an arbitrary time interval according to rate data. is there.

[0002]

2. Description of the Related Art A conventional rate generator is configured as shown in FIG. 3 is a counter, 2 is a match circuit, 3
Is a pulse generation circuit, 20 and 21 are D-type flip-flops, and 22 is an adder.

In FIG. 3, a counter 1 has a clock signal 31.
Is input, and counting is performed using this clock. The adder 22 receives the rate data latched by the rate signal 33 in the D-type flip-flop 20 and performs addition with the output of the D-type flip-flop 21 which is the immediately preceding addition result. The D-type flip-flop 21 inputs the output of the adder 22 to the data terminal, inputs the rate signal 33 to the clock terminal, and outputs the output to the adder 22 and the matching circuit 2.

[0004] The coincidence circuit 2 compares the N-bit output of the counter 1 with the N-bit output of the D-type flip-flop 21 and outputs a coincidence signal 34 to the pulse generation circuit 3. The pulse generation circuit 3 outputs the output of the coincidence circuit 2 and the clock signal 3
1 is input, and one pulse is generated by the clock when the coincidence signal is received. In this way, a pulse is generated every time the output value of the counter matches the output value of the adder, so that a desired rate signal can be obtained.

FIG. 4 is a timing chart of the prior art in FIG. In FIG. 4, A is a clock signal 31
, B is a waveform diagram of the output of the counter 1, C is a waveform diagram of the output of the D-type flip-flop 20, D is a waveform diagram of the output of the D-type flip-flop 21, and E is a waveform diagram of the rate signal 33. .

As shown in FIG. 4A, the period of the clock signal 31 is T. The counter 1 is counting up as shown in B of FIG. "2" in the rate data 32,
Consider a case where data is given in the order of “3”, “4”, and ‥‥.

The adder 22 is a D-type flip-flop 20
Are sequentially added, the output of the D-type flip-flop 21 becomes "1" + "2" = D as shown in D of FIG.
"3", "3" + "3" = "6", "6" + "4" =
It changes in the order of “10”, “10” + “5” = “15”.

When one input of the matching circuit 2 is "1",
Since they are "3", "6", "10", and "15", the counter 1 counts up and the counter output is "1",
When it becomes "3", "6", "10", "15",
The input of the matching circuit 2 matches, and the pulse generating circuit 3 generates a pulse as shown in FIG. 4E by the clock signal of FIG. In this way, rate signals 33 having time intervals of 2T, 3T, 4T, ‥‥ can be obtained.

[0009]

For example, in recent years, ICs
With the increase in the speed of, for example, the rate generator used in the IC tester also needs to set a rate signal with a wide time interval from a low-speed signal to a high-speed signal. As described above, when it is desired to set a rate signal with a wide time interval, the bit width N of the rate data increases, and the time required for addition increases, and when a high-speed rate signal is generated, the addition is performed within the rate time. There was a problem that it became difficult.

It is an object of the present invention to provide a rate generator capable of generating a rate signal having a wide range of time intervals from a low-speed signal to a high-speed signal.

[0011]

According to the present invention, an N-bit (N is a natural number) for counting an input clock signal 31 and outputting the count value is provided.
And a first adder 16 for pairing two consecutive rate data 32 and adding them, and a second adder 16 for pairing the rate data 32 shifted by one stage and adding them. , A third adder 18 for sequentially adding the result of the first adder 16, and a fourth adder 19 for sequentially adding the result of the second adder 17
A selector 4 for alternately selecting a result of the third adder 18 and a result of the fourth adder 19, an output of the counter 1 as a first input, an output of the selector 4 as a second input, A coincidence circuit 2 for detecting coincidence between the two and a pulse generation circuit 3 which receives an output of the coincidence circuit 2 and a clock signal 31 and outputs a rate signal 33 are provided.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the rate generator according to the present invention will be described in detail. FIG. 1 is a block diagram showing an embodiment of a rate generator according to the present invention. The rate generator according to the present embodiment is a circuit for generating a rate signal having an arbitrary time interval from a low-speed signal to a high-speed signal used in an IC tester or the like in accordance with the rate data. In FIG. 1, 1 is a counter, 2 is a coincidence circuit, 3 is a pulse generation circuit formed of a D-type flip-flop, 4 is a selector, 5 is a frequency divider, 6 to 15 are D-type flip-flops, and 16 to 19 are It is an adder.

In FIG. 1, a counter 1 has a clock signal 31.
, Is counted by this clock, and the result is sent to the coincidence circuit 2 as N-bit (N is a natural number) data. The rate data 32 is
D-type flip-flops 6 to 8 are input to data input terminals of a three-stage shift register,
Are stored in the D-type flip-flops 6 to 8 at the timing shown in FIG.

The outputs of the D-type flip-flops 6 to 8 are input to the data input terminals of the D-type flip-flops 9 to 11, respectively. It is latched by type flip-flops 9-11. The output of the D-type flip-flop 9 and the output of the D-type flip-flop 10 are added by an adder 16. Similarly, the output of the D-type flip-flop 10 and the output of the D-type flip-flop 11 are added by the adder 17.

The outputs of the adders 16 and 17 are input to data inputs of D-type flip-flops 12 and 13, respectively.
The signal obtained by dividing the rate signal 33 by the divider 5
Latched by D-type flip-flops 12 and 13.

The output of the D-type flip-flop 12 is input to an adder 18, and the adder 18 performs addition with the output of the D-type flip-flop 14, which is the immediately preceding addition result. Similarly, the output of the D-type flip-flop 13 is input to the adder 19, and the adder 19 performs addition with the output of the D-type flip-flop 15, which is the immediately preceding addition result.

The outputs of the adders 18 and 19 are input to data inputs of D-type flip-flops 14 and 15, respectively.
The signal obtained by dividing the rate signal 33 by the divider 5
Latched by D-type flip-flops 14 and 15.

The selector 4 has a D-type flip-flop 14
And the N-bit output of the D-type flip-flop 15 are selected by the signal obtained by dividing the rate signal 33 by the frequency divider 5 and sent to the coincidence circuit 2.

The coincidence circuit 2 compares the N-bit output of the counter 1 with the N-bit output of the selector 2, and outputs a coincidence signal to the pulse generation circuit 3 when these outputs coincide. The pulse generating circuit 3 receives the output of the matching circuit 2 and the clock signal 31 and generates one pulse by a clock when the matching signal is received.

In this manner, a pulse is generated each time the output value of the counter matches the output value of the selector, whereby a desired rate signal can be obtained.

FIG. 2 is a timing chart of the rate generator in the present embodiment shown in FIG. FIG. 2 shows an example in which the N bits shown in FIG. 1 are N = 5.
2, A is a waveform diagram of the clock signal 31, B is a waveform diagram of the output of the counter 1, C to L are waveform diagrams of the outputs of the D-type flip-flops 6 to 15, M is a waveform diagram of the output of the selector 4, N is a waveform diagram of the rate signal 33, and O is a waveform diagram of the output of the frequency divider 5.

As shown in FIG. 2A, the clock signal 31
Is T, the counter 1 counts up as shown in FIG. The rate data 32 includes “2”,
It is assumed that data is given in the order of “3”, “4”, and ‥‥. The rate data 32 is input to a three-stage shift register composed of D-type flip-flops 6 to 8 in FIG. 1 and becomes as shown in C to E in FIG.

The D-type flip-flops 9 to 11 in FIG.
The output of the D-type flip-flops 6 to 8 is latched every other signal by a signal obtained by dividing the rate signal 33 such as O in FIG. 2 by the frequency divider 5, and the waveforms of F to H in FIG. 2 are obtained.

Since the adder 16 adds the output of the D-type flip-flop 9 and the output of the D-type flip-flop 10, the output of the D-type flip-flop 12 becomes "3" + "2" as shown by I in FIG. = "5", "5" + "4" =
It changes in the order of “9”, “7” + “6” = “13”. Similarly, the adder 17 includes the D-type flip-flop 10
And the output of the D-type flip-flop 11 are added, so that the output of the D-type flip-flop 13 becomes "2" + "1" = "3", "4" + "3" as shown in J of FIG. =
It changes in the order of “7”, “6” + “5” = “11”.

The adder 18 is connected to the D-type flip-flop 12
Are sequentially added, and if the initial value of the output of the D-type flip-flop 14 is “1”, as shown in FIG.
"1" + "5" = "6", "6" + "9" like K
= Changing in the order of "15". Similarly, adder 19
Sequentially adds the outputs of the D-type flip-flops 13, so that the output of the D-type flip-flop 15 is "0" + as shown in L of FIG. 2 if the initial value is "0".
It changes in the order of “3” = “3”, “3” + “7” = “10”.

The selector 4 alternately selects the data of K in FIG. 2 and the data of L in FIG. 2 by O in FIG. 2 to obtain the waveform of M in FIG. One input of the match circuit 2 is “1”,
Since they are "3", "6", "10", and "15", the counter 1 counts up and the counter output is "1",
When the value becomes "3", "6", "10", or "15", the two input signals of the matching circuit 2 match. When the two input signals input to the input terminals match in this manner, the pulse generation circuit 3 generates a pulse as shown by N in FIG. 2 by the clock signal of A in FIG. In this way,
Rate signals 33 having time intervals of 2T, 3T, 4T, ‥‥ can be obtained.

In this embodiment, the rate generator which has only to perform the addition within the time corresponding to two rates is shown. However, the present invention is not particularly limited to this. The present invention can also be applied to a rate generator that performs addition within a period of more than one minute.

[0028]

According to the present invention, the addition can be performed within the time corresponding to two rates, so that a wide range of rate signals can be generated at any time interval from a low-speed signal to a high-speed signal. it can.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a rate generator according to the present invention.

FIG. 2 is a timing chart showing an operation example of the rate generator of FIG.

FIG. 3 is a rate generator according to the prior art.

FIG. 4 is a timing chart of the rate generator of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Counter 2 Matching circuit 3 Pulse generating circuit 4 Selector 5 Divider 6-15 D-type flip-flop 16-19 Adder

Claims (1)

(57) [Claims] 1. An N bit (N is a natural number) for counting an input clock signal (31) and outputting the count value.
Counter (1), two pairs of continuous rate data (32), a first adder (16) that adds them, and two pairs of rate data (32) shifted one stage And a third adder (1) that sequentially adds the results of the first adder (16).
8) and a fourth adder (1) for sequentially adding the results of the second adder (17).
9), a selector (4) for alternately selecting the result of the third adder (18) and the result of the fourth adder (19), and the output of the counter (1) as the first input, and the selector The output of (4) is used as the second input, the matching circuit (2) that detects the match between the two, the output of the matching circuit (2) and the clock signal (31) are input, and the rate signal (33) is output. And a pulse signal generating circuit (3), and a rate signal at a desired time interval according to the rate data (32).
A rate generator for generating (33).