JP2003037504A - Device for generating gray code - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for generating gray code, which can directly generate a gray code without generating a binary code and without reducing the maximum operating frequency even when the bit number of the gray code increases. SOLUTION: Shift registers are provided connecting D flip-flops 1 to 2, 3 to 6, and 7 to 14 in cascade respectively for gray code bits D0 to D2. The number of steps of each shift register (the number of D flips) is set according to the periodicity (the number of times that '0' or '1' is repeated), appearing in each bit of the gray code. Input terminals of the D flip-flops 2, 5 and 11 are connected to inverted output terminals of the D flip-flops 1, 4 and 10 in the former steps respectively so that '0's are output after the occurrence of the gray code until the appearance of the periodicity. Furthermore, to simplify the configuration of the device, an output terminal of the D flip-flop 10 set in the D2 bit provides the highest order bit (D3 bit).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Gray code generator for generating a Gray code.

[0002]

2. Description of the Related Art Generally, a binary system is used to represent a number (natural number) as a binary value consisting of "0" and "1", but a Gray code is known in addition to the binary system. There is. For example, when the numerical value "7" expressed in the decimal system is expressed in the binary system, it becomes "0111". In the binary system, if the number "1" is added to this value, it becomes "1000", and by adding "1", many digits may change at the same time.

However, in Gray code, it is always 1
It has the property that only one digit changes and the other digits do not change. That is, in the Gray code, the numbers of consecutive numbers are different by only one digit, and the other numbers are the same. Gray codes having such properties are often used in game solving methods and the like, and are also applied in various fields of computer science such as minimization of electronic circuits and image compression.

FIG. 5 is a block diagram showing a configuration example of a conventional Gray code generator. In FIG. 5, a 4-bit synchronous Gray code generator is shown as an example. The conventional Gray code generation device includes a binary code generation unit 50 that generates a binary code and a conversion unit 60 that converts the binary code output from the binary code generation unit 50 into a Gray code.

The binary code generator 50 includes D flip-flops 51, 53, 56 and 59, exclusive OR operation circuits (hereinafter referred to as EXOR circuits) 52, 55 and 58, and AND circuits (hereinafter referred to as AND circuits). 54 and 57 are provided. The clock CLK and the reset signal RST are input to the D flip-flops 51, 53, 56 and 59, and the inverting output terminal and the input terminal of the D flip-flop 51 are connected.

The EXOR circuit 52 calculates the exclusive OR of the output of the D flip-flop 51 and the output of the D flip-flop 53 and inputs the result as the input of the D flip-flop 53. The AND circuit 54 calculates the logical product of the output of the D flip-flop 51 and the output of the D flip-flop 53.
The EXOR circuit 55 calculates the exclusive OR of the output of the AND circuit 54 and the output of the D flip-flop 56, and uses it as the input of the D flip-flop 56.

The AND circuit 57 calculates the logical product of the output of the AND circuit 54 and the output of the D flip-flop 56.
The EXOR circuit 58 calculates the exclusive OR of the output of the AND circuit 57 and the output of the D flip-flop 59 and inputs it to the D flip-flop 59. The output terminals of the D flip-flops 51, 53, 56 and 59 are connected to the output terminals of the respective bits of the binary code generator 50.

As can be seen from the above description, k (k ≧
The D flip-flop of the 3rd stage has a signal indicating the logical product of the output of the D flip-flop of the (k-1) th stage and the output of the D flip-flop of the (k-2) th stage, and the k-th stage. Of D
A signal indicating an exclusive OR with the signal output from the flip-flop is input. Therefore, in order to invert the output of the k-th stage D flip-flop, it is necessary that all the outputs of the first-stage D flip-flop 51 to the (k−1) -th stage D flip-flop become “1”. .

The binary code generator 50 having the above-mentioned configuration receives the reset signal RST and receives the D flip-flop 5
The number of clocks CLK input after 1, 53, 56 and 59 are reset is counted, and the counted value is output as a 4-bit binary code including bits Q0 to Q3.

The conversion unit 60 includes EXOR circuits 61 to 63. The EXOR circuit 61 includes a binary code generator 50.
The exclusive OR of the signal of bit Q0 and the signal of bit Q1 of the binary code generated from Similarly, EX
The OR circuit 62 obtains the exclusive OR of the signal of the bit Q1 and the signal of the bit Q2, and the EXOR circuit 63 obtains the exclusive OR of the signal of the bit Q2 and the signal of the bit Q3.

As described above, the conversion circuit 60 has the bits Q0 to Q0.
Bits D0 to D are obtained by obtaining the exclusive OR of the adjacent bits of the 4-bit binary code composed of Q3.
Convert to a 4-bit Gray code consisting of 3. The correspondence between the binary code generated by the binary code generation unit 50 and the Gray code output from the conversion unit 60 is shown in FIG. FIG. 6 is a diagram showing an example of a correspondence table between binary codes and Gray codes.

[0012]

In the conventional Gray code generator shown in FIG. 5, the D flip-flops 51, 53, 53 provided in the binary code generator 50 are provided.
Although the outputs of 56 and 57 are used as binary codes, as described above, in order to invert the output of the D flip-flop of the kth stage, the D flip-flop 5 of the first stage is used.
The outputs of all D flip-flops in the 1st to (k-1) th stages must be "1".

This operation is performed by a plurality of AND circuits (for example,
AND circuits 54, 57) and a plurality of EXOR circuits (for example, EXOR circuits 52, 55, 58), the binary code generation unit increases as the number of bits of the binary code (the number of D flip-flop stages) increases. 5
There is a problem that the maximum operating frequency of the Gray code generator is lowered due to the increase of the delay time in the logic circuits (for example, EXOR circuits 52, 55, 58 and AND circuits 54, 57) provided in 0. It was

In the conventional apparatus shown in FIG. 5, after the binary code is generated by the binary code generator 50,
This is a two-stage configuration in which a binary code is converted into a gray code by the conversion unit 60. Therefore, in order to generate the Gray code, it is necessary to generate the binary code without fail, and there is a problem that the Gray code cannot be directly generated.

The present invention has been made in view of the above circumstances, and it is possible to directly generate a gray code without generating a binary code without lowering the maximum operating frequency even if the number of bits of the gray code is increased. An object of the present invention is to provide a Gray code generator capable of

[0016]

In order to solve the above-mentioned problems, a Gray code generator of the present invention is a shift register (1 to 2) having a number of stages of periodicity which appears for each bit of a Gray code consisting of a plurality of bits. 3-6, 7-14, 2
0 to 23, 30 to 33) for each bit of the gray code, and the shift register (1 to 2, 3) according to the change in the logic of each bit at the start portion of the gray code.
.About.6, 7 to 14, 20 to 23, 30 to 33), the input in a predetermined number of stages is changed bit by bit. According to the present invention, a shift register is provided for each bit of the gray code, the number of stages is set to the periodicity appearing for each bit of the gray code, and further, the input at the predetermined number of stages is logically performed for each bit of the gray code. The gray code can be generated without generating the binary code, because the gray code is changed according to the change of. Also,
The Gray code generator of the present invention is a shift register (1-2, 3-6, 7-14, 2 provided for each bit).
0 to 23, 30 to 33) are shift registers (1 to 2, 3 to 6, 7 to 14, 20 to 2 provided in other bits.
3, 30-33). According to the present invention, since the shift register provided for each bit of the gray code is operated independently of the shift register provided for the other bits, the maximum operation is achieved even if the number of bits of the gray code is increased. It is possible to prevent the frequency from decreasing. Further, the Gray code generator of the present invention is a shift register (1-2, 3-6, 7-14, 20-23, 30-3 provided for each bit.
It is preferable that 3) operates in synchronization with the reference clock (CLK). Also, in the Gray code generator of the present invention, the number of bits of the Gray code is changed from 0th bit to (N
-1) Assuming N bits (N is a natural number of 2 or more) up to the ^1st bit, 2 ^{m + 1} (0≤m≤N-2) stages for each bit from the 0th bit to the (N-2) th bit Of the shift registers (1-2, 3-6, 7-14, 20-23, 30-)
33) is provided. Further, in the Gray code generator of the present invention, the predetermined number of stages to which the input is changed is the 2 ^m +1 stage in each bit from the 0th bit to the (N-2) th bit of the Gray code. It is characterized by that. Still further, the Gray code generator of the present invention is (N-1) of the Gray code.
Bit ^{is, (N-2) 2 N} -2 stage shift register provided in the bit (7～14,30～33) (10,
31) is obtained from. Also, the Gray code generator of the present invention is a shift register (1-2, 3-6, 7-14, 20-2 provided for each bit).
3, 30 to 33), the output of the final stage is input to the first stage. In addition, the Gray code generator of the present invention is the shift register (1-2, 3-
6, 7 to 14, 20 to 23, 30 to 33) are configured by connecting D flip-flops in cascade.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a Gray code generator according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a Gray code generator according to an embodiment of the present invention. The gray code generating device shown in FIG. 1 is illustrated by taking a synchronous gray code generating device for generating a gray code of 4 bits D0 to D3 as an example.

As shown in FIG. 1, the gray code has a total of 4 bits of bits D0 to D3, and a shift register in which D flip-flops 1 and 2 are cascade-connected to the bit D0,
The bit D1 is provided with a shift register in which D flip-flops 3 to 6 are connected in cascade, and the bit D2 is provided with a shift register in which D flip-flops 7 to 14 are connected in cascade. A clock CLK is supplied to the D flip-flops 1 to 14.
The (reference clock) and the reset signal RST are supplied, and the D flip-flops 1 to 14 operate in synchronization with the clock CLK.

Further, in the shift register provided in the bit D0 of the Gray code, the output of the D flip-flop 2 in the final stage is used as the input of the D flip-flop 1 in the first stage, and in the shift register provided in the bit D1. ,
The output of the D flip-flop 6 at the final stage is used as the input of the D flip-flop 3 at the first stage, and in the shift register provided for the bit D2, the D flip-flop 14 at the final stage is used.
Is used as the input of the D flip-flop 7 in the first stage. This is to generate a periodic gray code (in the example shown in FIG. 6, decimal numbers “0” to “1”).
5 "is periodically generated).

The shift register provided in each bit D0 to D2 operates independently of the shift registers provided in other bits. In the conventional Gray code generator shown in FIG. 5, D flip-flops 51, 53, 56, 5 are used.
Although the binary code was obtained from the output of 9 and the binary code was converted into the Gray code in the arithmetic unit 60, in order to obtain the binary code (output of the D flip-flops 53, 56, 59), the EXOR circuits 52, 55 , 58,
The calculation in the logic circuits such as the AND circuits 54 and 57 is required.

The operations of these logic circuits are operations between bits of a binary code. For example, AND
The circuit 54 calculates the output of the D flip-flop 51 (bit Q0 of the binary code) and the output of the D flip-flop 53 (bit Q1 of the binary code). Therefore, the maximum operating frequency has been lowered because the calculation is conventionally performed between bits. In the present embodiment, as described above, the shift register provided in each bit D0 to D2 is operated independently of the shift registers provided in other bits to prevent the maximum operating frequency from decreasing.

Here, the number of stages of the shift register provided in the bits D0 to D2 will be described. Bits D0-D
The number of stages of the shift register provided in 2 is set in consideration of the periodicity of the Gray code. That is, to explain using the gray code shown in FIG. 6, the logic of the bit D0 of the gray code changes every time two numbers are counted, and the logic of the bit D1 changes every four numbers are counted, Bit D
The logic of 2 changes every time it counts eight numbers. In this embodiment, the number of stages of the shift register is determined by paying attention to the periodicity of the Gray code.

In the shift register provided in the bit D0, only the input of the D flip-flop 2 in the second stage is set to the inverted output of the D flip-flop 1 provided in the previous stage, and the shift provided in the bit D1 is set. In the register,
Only the input of the D flip-flop 5 in the third stage is set to the inverted output of the D flip-flop 4 provided in the previous stage, and in the shift register provided in the bit D2, the D register in the fifth stage is set.
Only the input of the flip-flop 11 is provided in the previous stage.
It is set to the inverted output of the flip-flop 10. This is set according to the change of logic for each bit in the start portion of the Gray code.

That is, to explain with reference to the Gray code shown in FIG. 6, there is a part where the periodicity is broken at the start portion of the Gray code before the above-mentioned periodicity of the Gray code appears. For example, in the case of bit D0 of the Gray code, a periodicity in which the logic changes every time two numbers are counted after outputting "0" once, and in bit D1 four "0" is output after outputting "0" twice. The periodicity that the logic changes each time the number is counted appears, and "0" is set to 4 in bit D2.
A periodicity in which the logic changes every time the eight numbers are counted after the output is repeated appears. As described above, the periodicity is partially broken at the start portion of the gray code, and in order to realize the breaking of the periodicity, the inputs of the D flip-flops 2, 5 and 11 are connected to the D flip-flops 1, 4 of the preceding stage. 10 inverted outputs are set respectively.

Further, the D3 bit of the Gray code is obtained from the output of the D flip-flop 10 of the shift register provided in the bit D2. A shift register can be provided for the bit D3 as in the case of the other bits D0 to D2, but in this embodiment, the shift register is used as the output of the D flip-flop 10 in order to simplify the circuit configuration.
Focusing on the gray code bit D3 shown in FIG. 6,
The periodicity that appears in the bit D3 is the same as the periodicity that appears in the bit D2, and the other bits D0 to D are included in the bit D3.
Since there is no break in the periodicity at the beginning of the Gray code appearing in 2, it is possible to omit the shift register and use the shift register provided in bit D2.

FIG. 2 is a table showing truth values of the Gray code generator according to the embodiment of the present invention, and FIG. 3 is a timing chart of the Gray code generator according to the embodiment of the present invention. In the timing chart shown in FIG. 3, when the reset signal RST is input, all the D flip-flops 1 to 14 are reset, and the outputs q1 to q14 of the D flip-flops 1 to 14 are all "0". However, since the inputs of the D flip-flops 2, 5, 11 are the inverted outputs of the D flip-flops 1, 4, 10 at the preceding stage, only the D flip-flops 2, 5, 11 among the D flip-flops 1-14 are provided. The signal of "1" is input.

Therefore, when the first clock CLK is input, the output q2 of the D flip-flop 2 (Gray code bit D0), the output q5 of the D flip-flop 5,
And the output q11 of the D flip-flop 11 becomes "1".

With respect to the shift register provided in the bit D0, when the second clock CLK is input, the output q2 of the D flip-flop 2 (Gray code bit D
0) remains "1", but the inverted output of the D flip-flop 1 becomes "0". Therefore, the third clock C
When LK is input, output q2 of D flip-flop 2
(Gray code bit D0) becomes "0". Or later,
By performing such an operation, the shift register provided in the bit D0 becomes a signal whose logic is inverted every time two clocks CLK are input.

Further, regarding the shift register provided in the bit D1, since "1" is input to the input end of the D flip-flop 6 at the time when the second clock CLK is input, The output q6 (Gray code bit D1) becomes '1'. When the output q6 of the D flip-flop 6 (bit D1 of the gray code) becomes "1", "1" is input to the input end of the D flip-flop 3, and the output q3 of the D flip-flop 3 at the third clock CLK. Will be '1'. As a result, 4
The inverted output of the D flip-flop 4 becomes "0" at the sixth clock, the output of the D flip-flop 5 becomes "0" at the fifth clock, and the output q6 of the D flip-flop 6 (gray code) at the sixth clock. Bit D1)
Will be '0'. After that, by performing such an operation, the shift register provided in the bit D1 becomes a signal whose logic is inverted every time four clocks CLK are input.

With respect to the shift register provided in the bit D2, the output q11 of the D flip-flop 11 becomes "1" at the time when the first clock CLK is input, so that at the time when the fourth clock CLK is input. Therefore, the output q14 (Gray code bit D2) of the D flip-flop 14 becomes "1". Since the output q14 of the D flip-flop 14 is input to the D flip-flop 7,
Thereafter, every time the clock CLK is input, the outputs q7, q8, q9 of the D flip-flops 7, 8, 9 sequentially become “1”, and when the eighth clock is input, the output q10 of the D flip-flop 10 (gray Code bit D3)
Becomes '1'.

When the output q10 of the D flip-flop 10 (bit D3 of the gray code) becomes "1", the inverted output of the D flip-flop 10 becomes "0", so that the D flip-flops are sequentially input each time the clock CLK is input. 1
Outputs q11, q12, q13 of 1, 12, 13 are "0"
Thus, the output q14 (Gray code bit D2) of the D flip-flop 14 becomes "0" when the twelfth clock is input. This output q14 is input to the D flip-flop 7, and each time the clock CLK is input thereafter, the output q7 of the D flip-flops 7, 8, 9 is sequentially output.
q8 and q9 become "0", and the output q10 (Gray code bit D3) of the D flip-flop 10 becomes "0" when the 16th clock is input. By the above operation, the Gray code shown in FIG. 6 is generated.

In the above description, the synchronous gray code generator for generating the gray code of 4 bits D0 to D3 has been taken as an example, but the present invention generates the gray code of any bit number of 2 bits or more. It can be applied to a Gray code generator. FIG. 4 shows N (N is a natural number of 2 or more)
It is a figure which shows the structure of the Gray code generator which generate | occur | produces the Gray code of bit. The Gray code generator shown in FIG. 4 generates a Gray code of N bits of D0 to D (N-1) bits.

As shown in FIG. 4, the shift register provided for the D0 bit has the same structure as that shown in FIG.
The number of stages of shift registers (the number of D flip-flops) provided in the Dm bits (0 ≦ m ≦ N−2) from the 0th bit to the (N−2) th bit is 2 ^{m + 1} . The D flip-flop 20 shown in FIG. 4 is the first stage, and the D flip-flop 23 is the 2 ^{m + 1} stage. Also, D (N-
2) The D flip-flop 30 provided for each bit is the first stage, and the D flip-flop 33 is the 2 ^N−1 stage.

Further, in the shift register provided in the Dm-bit, the input terminal of the inverting output terminal and 2 ^m +1 stage D flip-flop of 2 ^m-th stage D flip-flop is connected. The D flip-flop 21 shown in FIG.
^{It is the mth} stage, and the D flip-flop 22 is the ^2m + 1th stage. The D flip-flop 31 provided in the D (N−2) -th bit is the 2 ^N−2 stage and the D flip-flop 32 is the 2 ^N−2 +1 stage. Furthermore, the (N-1) th bit of the Gray code is the ^2N-2th stage of the shift register provided at the (N-2) th bit, that is, D in FIG.
It is obtained from the output of the flip-flop 31.

In the gray code generator having the configuration shown in FIG. 4, even if the number of bits of the gray code increases, the shift register provided for each bit operates independently of the shift registers provided for other bits. Therefore, the maximum operating frequency is not lowered. Also, the Gray code generator shown in FIGS. 1 and 4 can directly generate a Gray code without generating a binary code. In the embodiments described above, the case where a circuit is configured has been described as an example, but the present invention can be applied to a case where it is realized by software.

[0036]

As described above, according to the present invention,
A shift register is provided for each bit of the gray code, the number of stages is set to the periodicity that appears for each bit of the gray code, and the input at a predetermined number of stages changes according to the change of the logic for each bit of the gray code. Therefore, there is an effect that the gray code can be generated without generating the binary code. Further, according to the present invention, since the shift register provided for each bit of the gray code is operated independently from the shift register provided for the other bits, even if the number of bits of the gray code increases. There is an effect that it is possible to prevent a decrease in the maximum operating frequency.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a Gray code generator according to an exemplary embodiment of the present invention.

FIG. 2 is a table showing truth values of a Gray code generator according to an exemplary embodiment of the present invention.

FIG. 3 is a timing chart of a Gray code generator according to an exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a Gray code generation device for generating a Gray code of N bits (N is a natural number of 2 or more).

FIG. 5 is a block diagram showing a configuration example of a conventional Gray code generator.

FIG. 6 is a diagram showing an example of a correspondence table between binary codes and Gray codes.

[Explanation of symbols]

1, 2 D flip-flop (shift register) 3-6 D flip-flop (shift register) 7 to 14 D flip-flop (shift register) 20-23 D flip-flop (shift register) 30-33 D flip-flop (shift register) CLK clock (reference clock) RST reset signal

Claims (8)

[Claims] 1. A shift register having a number of stages corresponding to a periodicity that appears for each bit of a gray code composed of a plurality of bits is provided for each bit of the gray code, and the shift register responds to a change in logic for each bit at a start portion of the gray code. The gray code generator is characterized in that the input at a predetermined number of stages of the shift register is changed bit by bit. 2. The Gray code generation device according to claim 1, wherein the shift register provided for each bit operates independently of the shift registers provided for other bits. 3. The Gray code generator according to claim 1, wherein the shift register provided for each bit operates in synchronization with a reference clock. 4. When the number of bits of the Gray code is N bits (N is a natural number of 2 or more) from 0th bit to (N-1) th bit, the shift register starts from 0th bit to (N-2). ) 2 ^{m + 1} (0 ≦
The gray code generator according to claim 1, wherein m ≦ N−2) stages are provided. 5. The predetermined number of stages in which the input is changed is the 2 ^m +1 stage in each bit from the 0th bit to the (N−2) th bit of the Gray code. Item 4. The Gray code generator according to item 4. 6. The (N-1) th bit of the Gray code is obtained from the ^2N-2th stage of the shift register provided at the (N-2) th bit. Item 5. The Gray code generator according to item 5. 7. The Gray code according to claim 1, wherein the shift register provided for each bit has the output of the final stage input to the first stage. Generator. 8. The Gray code generation device according to claim 1, wherein the shift register is configured by connecting D flip-flops in a cascade manner.