JPS62192097A - Shift register circuit - Google Patents

Abstract

PURPOSE:To change an output signal at half of its period without adding a special circuit by connecting the inverse of the output terminal Q of a flip flop D at the preceding stage to the input terminal d of the flip flop D. CONSTITUTION:The output signals Q'A and Q'B of the 1st and 3rd staged D-Fs 11A and 11C and the output signals Q'B and Q'D of the 2nd and fourth D-F/Fs 11B and 11D and initialized to a logic '1' and a logic '0', respectively. If under this state, a data signal D to input D of the F/F 11A changes to a logic '1' the output signals Q'A, Q'B, Q'C and Q'D change at 1/2 frequency of a clock signal C in synchronization with the clock signal C. Namely, the signals Q'A-Q'D can change at the 1/2 period of the signal C without adding a special circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a shift register circuit that is a component of a ring counter or the like, and more particularly to a shift register circuit constructed by combining D flip-flops.

BACKGROUND ART In general, shift register circuits are widely used in digital circuits, and are particularly frequently used as ring counters that output timing signals with a constant period. Conventionally, as this type of shift register circuit, a circuit shown in FIG. 6 or a circuit shown in FIG. 8 which is applied as a ring counter are known.

The former shift register circuit, as shown in FIG. 6, consists of four D flip-flops (hereinafter abbreviated as L-FyF) (IIA
) CIIB) (11 (IID) (hereinafter represented by numbers without subscripts) are arranged in 4 stages, m1 stage L) -k
>h・<11) Q output terminal is connected to the subsequent D-F/F(u)
It is connected to the D input terminal of. As shown in the timing chart in Figure 7, this shift register circuit is designed for each D-1 data signal input to the D input terminal of the first stage L)-F'/F (IIA). /F(llA
) (11B) (110) (IID) output signal (
QA) (LaB) (Qo) (Qo) (hereinafter represented by a code without a subscript) changes. Note that the timing chart in FIG. 7 represents the case where all D-F//Fs (11) are initialized to output signals (L such that Q becomes logic O).

The latter ring counter is constructed based on the constant shift register circuit described above. That is, as shown in FIG. 8, this ring counter is connected to the D-input groove of the first-stage iJ-F//F (11 people) of the shift register circuit described above and the D-stop of the fourth stage. Connect the Q output terminal of F' (IID) and connect the first stage D-F/F' (11
Similarly, connect the S (set) terminal to which the initial signal is input to the second to fourth stage D-F//f11 (IIs).
(llo) (lln) is set as a reset terminal to which the initial signal (1) is input. As shown in the timing chart of FIG. 9, this ring counter operates on the initial signal (I) and each D-''/
The output signal of F'(11) (Q changes. That is, the ring counter modifies the array (QA QB QOQD ) of the output signal of each t>-J?F(u>) to represent the hexadecimal → sign. Then, the displayed hexadecimal to code transitions as shown in FIG.

Problems that this invention attempts to solve〉However,
In the conventional shift register circuit shown in FIG. 6, the period of the output signal Q is determined by the period of the clock signal (0), and the period of the output signal is determined by the clock signal (C).
In order to reduce the period to 1/2, another circuit must be added, and the problem is that there is no freedom to select the period of 1 and 0 to be output.

Furthermore, in the ring counter shown in FIG. 8 which is constructed from such a conventional shift register, the initial signal (
1), the problem is that the state of the change in the output signal (Q) is not determined unless the initial state is completely determined. Since it is possible to adopt five transition states represented by the 16M codes shown in (a) to (e) in Figure 11,
It is essential to provide an initial signal for initialization, and the accompanying circuitry may become complicated.

A shift register circuit according to the present invention was created in view of the above problems, and consists of L) 71J tube 70 tube that operates on the rising edge of the clock signal and the 70 tube that operates on the rising edge of the clock signal. It is constructed by arranging a large number of stages of D flip-flops that operate on the down edge in an alternating manner, and connecting all the Q output terminals of the D flip-flops in the previous stage to the D input terminals of these D flip-flops.

<Example> Embodiments of the present invention will be described below based on the drawings.

1 and 2 show a shift register circuit according to an embodiment of the present invention, with FIG. 1 being a circuit diagram and FIG. 2 being a timing chart.

As shown in Figure M1, this shift register circuit operates on two D-1 pins (I
IA) (110) It is constructed by alternately arranging two D-pins F (IIB) (LID) that operate on the downlink of O, T and LM) f in four stages. Clock signal (C
) of the first stage LJ-P/F (11B) whose Q output terminal operates at the rising edge of the clock signal (C). D input terminal, and in the same way, the second stage 1)-1-F
The q output terminal of (IIB) is connected to the third stage D”/F(l
3rd stage D-F/F (110
)'s Q output terminal is the fourth stage l) ”/F'(lln
) is connected to the D input terminal of the

This simple shift register circuit is constructed as shown in Fig. 2.
the output signal (QA) (QO) of lo) is deleted to 1, and
2nd and 3rd row D-F/F' (IIB) (11D
) output signals (QB) (QD) are initially set to logic 0, when the data signal - input to the D input terminal of the first stage D"/F (11A) changes to logic 1. , each output signal (QA) <Qs) (Qo) (Qo) is synchronized with the clock signal 1 (C) and the clock signal ((-'l
It changes in 1/2 cycle. In other words, this shift register circuit can handle the output signal (
QA) (QB) (Qo) (QD) can be changed at 1/2 of the period of the clock signal L').

3 to 5 show shift register circuits according to other practical IM examples of the present invention. This actual 7M example is an application of a shift register circuit to a ring counter. It should be noted that the same parts as those of the shift register circuit of FIG.

In Fig. 3, (12) is a NOR gate, and one of the two input terminals of this NOR gate (12) is connected to the Q output terminal of the fourth stage D-F/F (11D), and the other is connected to the Q output terminal of the fourth stage D-F/F (11D). The clear signal is input, and the output terminal is D of the first stage.
-F/)', is connected to the D input terminal of (uA).

The ring counter constructed based on this simple shift register circuit operates in units of four periods of the clock signal (C), and as shown in the timing chart of FIG. When the clock signal ((1) is input, the output signal (Q) of each DF/F (11) changes sequentially in two cycles. That is, each DF/F (
11) with the output signal array (QA QB QOQD)
When explained using the hexadecimal code 't & eagle, it is clear that eight states change in 1/2 period of the clock signal (U), as shown in FIG. In addition, FIG. 4 mentioned above shows the initial values (QA, QB,
QO2QD) k (1, O, 1, 0) (A in hexadecimal code) is set.

On the other hand, this ring counter has eight shapes of 7m when the power is turned on.
(01(8)(C1(E)(7)(1”)(1)(3
), but no matter which of these eight states is set at the time of initialization, simply inputting the clock signal L') sets the initial value (A) as described above, and the transition ( For convenience, this is referred to as normal transition). That is, as shown in FIG. 5, when state B (0) (8) is set, the state transitions to state (2) and normal transition occurs, and similarly, state (
q(When the average is set, after state (4), state (7)(
When L'l is set, state B (after Lll, state D (1)
When (3) is set, a normal transition occurs after the state (equal). Therefore, initialization is not necessarily necessary, and the circuit for initialization can be omitted.

<Effects> As explained above, the advantage of the shift register circuit according to the present invention is that the output signal can be changed at 1/2 of the period of the clock signal without adding any special circuit. 1. Since the ring counter constructed based on the shift register circuit according to the present invention guarantees a constant transition state regardless of whether it is initialized, there is no need to provide an initial signal, etc., and the accompanying circuit The entire simplification can be achieved.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 show a shift register circuit according to an embodiment of the present invention, with FIG. 1 being a circuit diagram and FIG. 2 being a timing chart. From Figure 3! Figure 5 shows a shift register circuit according to another example of the present invention, Figure 3 is a circuit diagram of a ring counter constructed based on the shift register circuit, Figure 4 is a timing chart, and Figure 5 shows a transition diagram. It is a diagram expressed in hexadecimal code. Figure 6 shows a conventional shift register circuit.
The figure is a timing chart. Figures 8 to 11 show a ring counter constructed based on a conventional shift register circuit, where Figure 8 is a circuit diagram, Figure 9 is a timing chart, and Figure 10 is a diagram showing transitions using 16 symbols. , Figures 11(a) to (e) show the transition when the initial value is not determined.
It is a diagram expressed in hexadecimal code. 11A, 11B, 110. IID =...-D flip-flop, D...input terminal, Q...output terminal, C...
Clock terminal (ricff clock signal), QA, QB, QO
,QD -output signal XkL/,it
·tree.

Claims (1)

[Claims] D flip-flops that operate on the rising edge of the clock signal and D flip-flops that operate on the falling edge of the clock signal are arranged in multiple stages alternately, and the D input terminal of these D flip-flops is connected to the @ of the D flip-flop in the previous stage.
A shift register circuit characterized in that a Q@output terminal is connected.