JP2968629B2 - Maximum period sequence code generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a maximum periodic sequence code such as a PN code used as a transmission path test signal for communication equipment, and more particularly to a circuit having a maximum of n stages (n: an arbitrary natural number). The present invention relates to a maximum-period sequence code generation circuit that can obtain a code according to the generator polynomial by supplying arbitrary code generation polynomial coefficient information to the circuit.

[0002]

2. Description of the Related Art An example of a conventional maximum period sequence code generation circuit will be described with reference to FIG. Conventionally, as shown in FIG. 3, a circuit for obtaining a plurality of types of maximum period sequence codes is provided for each code that generates a circuit for generating a target maximum period sequence code. That is, in the example of FIG. 3, the PN three-stage generation circuit 61, the PN four-stage generation circuit 62,
PN5 stage generation circuit 63, PN14 stage generation circuit 64, PN
The 15-stage generation circuit 65 corresponds to this. In addition, the configuration has the selector 7 for switching the signal generated individually for each code. 8 is a selector control signal input terminal and 9 is an output terminal.

[0003]

The conventional maximum period sequence code generation circuit has a generation circuit for each target code to be generated. In this case, although the basic configuration of the generation circuit does not change, shift registers must be prepared in the same number as the sum of the number of stages of the maximum period sequence code to be generated. Therefore, there has been a problem that the circuit scale increases as the types of desired codes increase.

[0004]

According to the maximum period sequence code generation circuit of the present invention, a flip-flop is connected to one input terminal of a 2-1 selector, and a signal retimed by a clock is input to the other input terminal. The input terminal comprises a register capable of directly inputting a signal without retiming, and the output of this register is connected to the input terminal of another register having the same configuration via a flip-flop. , Cascade-connected registers of n stages, n + 1 external input terminals, and Y _i = Y when the external input terminals are X _i (i = 0, 1,..., N). n _-1 inputs X _i-1 (i = 1, 2,..., n) which can be expressed as _i-1 + X _i-1 (i = 1, 2,..., n; Y ₀ = 0) ) and n output _{Y i (i = 1,2, ···} , n) and the first combination circuit with said n-stage shift MSB in the register (the input side)
The output of the register is set to S ₁ and the LSB side (output side) is sequentially
_{S 2, S 3, Z i} = bar _{Z i-1 · (X i} · Y i · S i) when the register output definition pickled LSB and ... was S _n Toward
+ Z _i-1 · bar _{(X i · Y i · S} i) (i = 1,2, ···, n; Z 0 = 0) among the functions represented, can be obtained Z _n comprising output and a second combination circuit, in registers forming the n-stage shift register, the input selection control terminal of the output S _i is connected to the output Y _i of said first combination circuit,
The input terminal of the person who does not perform retiming of the registers of the input terminals connected to the output Z _n of the second combination circuit and the Z _n to the input terminal of the person performing the retiming registers MSB The output is connected, and the output of the shift register is connected to an external output terminal.

[0005]

In the present invention, the first combination circuit has a function of determining a register in a shift register to be used for code generation from the degree of the generator polynomial. That is, when generating the m-th maximum periodic sequence code, “0” is input from the input terminals X ₀ to X _nm, and “1” is input to the corresponding terminal from X _nm to X _n according to the generating polynomial.
Is entered. Therefore, the output to the first combinational circuit is Y
_{From 0} to Y _nm-1, it becomes “0”, and from Y _nm to Y _n, it becomes “1”. Therefore, if the selector of the shift register is controlled by this, as many shifts as necessary according to the order of the generator polynomial are performed. Registers can function.
The second combination circuit has a function for generating a code according to the generator polynomial.

[0006]

FIG. 1 is a circuit diagram showing an embodiment of a maximum period sequence code generation circuit according to the present invention. Here, n = 15
As an example, a circuit that can generate a maximum period sequence code of up to 15 stages is shown. FIG. 2 is a circuit diagram in which a portion related to a register constituting the shift register in FIG. 1 is extracted and shown. 2, reference numeral 20 denotes a register constituting the shift register in FIG. 1, reference numeral 201 denotes a flip-flop, and reference numeral 202 denotes a 2-1 selector. And S = 0:
Y ← A, S = 1: Indicates Y ← B.

In FIG. 1, reference numeral 1 denotes a generator polynomial coefficient input terminal which is n + 1 external input terminals;
A flip-flop 201 is connected to one input terminal of one selector 202 to input a signal retimed by a clock, and the other input terminal includes a register capable of directly inputting a signal without retiming, This register output is connected to an input terminal via a flip-flop of another register having the same configuration, and an n-stage shift register in which n registers are cascade-connected, and 3 has n + 1 external input terminals 1 connected to X _i ( i = 0,1, ...,
n) and Y _i = Y _i-1 + X _i-1 (i = 1,2, ..., n; Y ₀ = 0)
N inputs X _i-1 (i = 1, 2,..., N) that can be expressed as
The first combinational circuit having n and n outputs Y _i (i = 1, 2,..., N) outputs the output of the MSB side (input side) register of the n-stage shift register 2 to S _1, and sequentially defined as S ₂ , S ₃ ,... Toward the LSB side (output side).
Z _i = bar Z _i-1 · when the register outputs of the set to S _n
(X _i · Y _i · S _i ) + Z _i-1 · bar (X _i · Y _i · S _i ) (i = 1, 2, ...,
n; Z ₀ = 0), the second combinational circuit 5 capable of obtaining an output of Z _n is an external output terminal.

[0008] Then, in registers forming the n-stage shift register 2, the input selection control terminal of the output S _i connect the output Y _i of the first combination circuit 3, a retiming of the input terminals of the register the input terminal of the person who is not performed to connect the output Z _n of the second combination circuit 4, further MSB
To the input terminal of the person performing the retiming of registers connected to the Z _n output, it is configured to connect the output of the shift register to the external output terminal 5.

Here, the first combination circuit 3 has a function of determining a register in a shift register to be used for code generation from the order of the generator polynomial. That is, m
When generating the next maximum period sequence code, from the input terminal X ₀ to X _nm is inputted is "0", "1" is input to the terminal corresponding according generator polynomial among than X _nm to X _n You. Therefore, the output of the first combination circuit 3 is Y ₀
To Y _nm-1 is “0”, and from Y _nm to Y _n is all “1”. By controlling the shift register selector by this, as many shift registers as necessary according to the order of the generator polynomial are obtained. Can function.
The second combination circuit 4 has a function for generating a code according to a generating polynomial.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. First, the 2-1 selector 2 shown in FIG.
02 is connected to one input terminal of the flip-flop 201 to form a two-input register 20, and the register 20 is cascaded by connecting the output of this register 20 to the input terminal of another register via the flip-flop. By doing so, the n-stage shift register 2 is configured.

Next, the coefficients of the generator polynomial of the code to be generated are input to X ₀ to X ₁₅ of the generator polynomial coefficient input terminal 1 which is n + 1 external input terminals. At this time, the coefficient of X ⁱ of the m-th generation polynomial is input to X _15-1 . Then, in the first combination circuit _{3, Y i = Y i-} 1 + X i-1 (i = 1,2 the X ₁₄ as input from the X ₀ of the generator polynomial coefficient input terminal 1, -
.., 15; Y ₀ = 0) and outputs Y ₁ to Y ₁₅ . For example, when the maximum period sequence code is generated according to the generator polynomial of X ⁷ + X ³ +1, “1” is input from the generator polynomial coefficient input terminal 1 only to X ₈ , X ₁₂ , and X ₁₅ , and “0” is input to the other. Is entered. In the case of such an input, an output of the first combination circuit 3 is Y ₀ to Y ₇ are the Y ₈ to Y ₁₅ at "0" becomes "1". This output is input to the selector control of the 2-1 selector 202 constituting the register 20 shown in FIG. In this register, when the selector control input is “1”, the input via the flip-flop 201 is selected, and when the selector control input is “0”, the signal directly input to the 2-1 selector 202 is selected. That is, the first combination circuit 3 performs control to make m registers out of n-stage shift registers valid according to the m-th generation polynomial.

[0012] Next, a second combination circuit 4, a shift register MSB and S _1, Z the LSB when the S _{15 i} = bar _{Z i-1 · (X i} · Y i · S i ) + Z _i-1 · bar (X _i · Y
_i · S _i ) (i = 1, 2,..., 15; Z ₀ = 0)
It is a circuit that can obtain ₁₅ outputs. Where Y
By taking the AND of _i and S _i , a shift register output of order m or less can be obtained, and by taking the AND of X _i , the coefficient of each order can be obtained according to the generator polynomial. Then, all the coefficients of each order are EXO
If R is taken, a code according to the generator polynomial can be generated. The output of the second combination circuit 4 is input to the two input terminals of the MSB register of the n-stage shift register 2 and to the input terminals of all registers constituting the shift register that do not pass through the flip-flops. With the above configuration, by inputting the coefficient information of the generator polynomial to the circuit from the input terminal, it is possible to generate an arbitrary maximum period sequence code of n stages or less.

[0013]

As described above, according to the present invention, a maximum period sequence code of n stages or less is generated by giving its coefficient by an n-stage shift register and a peripheral combination circuit. Since it is only necessary to prepare a number of shift registers and some combination circuits, there is an effect that the circuit scale can be significantly reduced as the number of desired code types increases as compared with conventional circuits. Further, the present invention has an effect that a general-purpose circuit for generating a maximum periodic sequence code can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a maximum period sequence code generation circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a register included in an n-stage shift register in FIG. 1;

FIG. 3 is a circuit diagram showing an example of a conventional maximum period sequence code generation circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 generator polynomial coefficient input terminal (external input terminal) 2 shift register (N-stage shift register) 3 first combination circuit 4 second combination circuit 5 external output terminal 20 register constituting shift register 2 201 flip-flop 202 2-1 selector

Continuation of front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H03K 3/84

Claims (1)

(57) [Claims] A 2-1 selector has a flip-flop connected to one input terminal to input a signal retimed by a clock, and another input terminal to directly input a signal without retiming. An n-stage shift register in which n (N: an arbitrary natural number) registers are connected in cascade, the output of this register being connected to an input terminal via a flip-flop of another register having the same configuration; When n + 1 external input terminals and X _i (i = 0,1,..., n) are used as the external input terminals, Y _i = Y _i-1 + X _i-1 (i = 1,2,. ···, n; Y ₀ = 0) and n inputs X _i−1 (i = 1,2,..., N) and n outputs Y _i (i = 1,2, .., N);
In the n-stage shift register, the output of the register on the MSB side (input side) is defined as S _1, and sequentially defined as S ₂ , S ₃ ,... Toward the LSB side (output side), and the register output of the LSB is defined as S _n. And Z _i = bar Z _i−1 · (X _i · Y _i · S _i ) +
Z _i-1 · bar _{(X i · Y i · S} i) (i = 1,2, ···, n; Z 0 = 0) of the represented functions in, capable of obtaining a Z _n comprising output A second combinational circuit, wherein the register constituting the n-stage shift register has an output The input selection control terminal of the S _i is connected to the output Y _i of said first combination circuit, to the input terminal of the person who does not perform retiming of the registers of the input terminal and the output of said second combination circuit connect the Z _n, further also connected to the Z _n output to the input terminal of the person performing the retiming of registers of the MSB, it is characterized in that so as to connect the output of the shift register to the external output terminal Maximum period sequence code generation circuit.