JP2833885B2 - PN code generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN code generation circuit for generating a plurality of types of PN codes and selectively outputting the generated PN codes.

[0002]

2. Description of the Related Art In a conventional PN code generation circuit, n kinds of P
When generating N codes, n shift register groups corresponding to each code type are used. FIG.
FIG. 3 is a diagram illustrating a configuration of a conventional PN code generation circuit that generates various types of PN codes. The first PN code (PN9 in this example)
Stage), a shift register 701, an exclusive OR circuit 801, and a second PN code (P in this example)
N11 stages), a shift register 702, an exclusive OR circuit 802, and a shift register 70 for generating a third PN code (in this example, PN15 stages).
3, an exclusive OR circuit 803, a shift register 704 for generating a fourth PN code (in this example, 20 stages of PN), an exclusive OR circuit 804, and a fifth P
A shift register 705 for generating an N code (in this example, PN23 stages) and an exclusive-OR circuit 805 have a total of five shift register groups.
The PN code which is input to the selection circuit 90 and selected by the externally input selection control signal input 70 is output to the PN code output terminal 60.

[0003]

However, in the above-described conventional PN code generation circuit, the same number of shift registers as the types of PN codes to be generated are required. Therefore, as the types of PN codes increase, the number of shift registers also increases. There is a disadvantage that the circuit scale increases.

The present invention solves such a conventional problem, and divides and uses one shift register having a length corresponding to the generation of the maximum number of stages of PN codes regardless of the number of types of PN codes. It is another object of the present invention to provide a PN code generation circuit capable of generating a plurality of types of PN codes.

[0005]

To achieve the above object, according to the solution to ## in the present invention, the PN code generating circuit for generating n different PN codes, the number of stages of each of the PN code to be generated m _i ( i = 1, 2,..., n; m _i > m
_i-1 ; m ₀ = 0), then n for every m _i -m _i-1 stage
From a shift register divided into pieces and a parallel input of each of the _mn element registers constituting the shift register and a coefficient input of a generator polynomial input from the outside,
A decoder for generating a signal to be serially input to the shift register; and n-1 2 → 1 selection circuits, and an output of the decoder is one input of each of the n-1 2 → 1 selection circuits. Terminal and msb of the n-th shift register, and the other input terminal of each of the j (j = 1,..., N−1) -th 2 → 1 selection circuits is connected to the (j + 1) -th shift register. Lsb output is input, and each output of the j-th 2 → 1 selection circuit is j
The second shift register is connected so as to be input to the msb of the shift register, and is connected to the second by the digit number information input from the outside.
→ Control the selection of the 1 selection circuit.

[0006]

Since the present invention is constructed as described above, by selecting the number of stages of the PN code to be generated based on the digit number information, the PN code determined by the coefficient input can be generated.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram showing a configuration in one embodiment of the present invention when n = 5. A case in which the same PN code as in FIG. 3 is generated will be described for easy comparison with the conventional example shown in FIG. That is, the number of stages of each of the PN code to be generated _{m i (i = 1,2, ...} , 5; m i> m i-1;
m ₀ = 0), m ₁ = 9, m ₂ = 11, m ₃ =
15, m ₄ = 20 and m ₅ = 23. 101,10
2,103,104, and 105, respectively m _i -
_i divided into five (i = 1, 2,...,
5) is the shift register, and the number of stages of each shift register is m ₁ −m _O = 9 for the first, and m ₂ −m _{1 for the second.}
The second and third are m ₃ −m ₂ = 4, the fourth is m ₄ −m ₃ =
The fifth and fifth are m ₅ -m ₄ = 3. The element registers of the shift register are 1 to 23 in order from lsb to msb.
The numbers up to are given. 201, 202, 203 and 204 are the i-th (i = 1, 2,..., 4) second
→ 1 selection circuit, and one input (lower side in the figure) has (i + 1) th shift registers 102, 103,
The lsb outputs of 104 and 105 are input, and the respective outputs are input to the msb of the i-th (i = 1, 2,..., 4) -th shift registers 101, 102, 103 and 104. Reference numeral 30 denotes a decoder to which an output of each element register j (j = 1, 2,..., 23) and a coefficient input of a generator polynomial are input in parallel from a coefficient input terminal 40, respectively. The output of the decoder 30 is a 2 → 1 selection circuit 20
1, 202, 203, and 204 each having the other input (upper side in the figure) and the fifth shift register 105.
Is input to the element register 23 which is the msb. 2 → 1
Digit number information is input from the digit number information input terminal 50 to control inputs of the selection circuits 201, 202, 203, and 204, respectively.

Next, the operation of the above embodiment will be described. 2 → 1 selection circuits 201, 202, 203 and 20
Reference numeral 4 denotes shift registers 102, 103, 104, and 105 when the digit number information as a control input is "1".
This is a switching circuit that outputs lsb and outputs the output from the decoder 30 when it is "0". Therefore, the number of stages of the shift register required for generating the PN code can be adjusted depending on how the digit number information is given. . Therefore, when generating a nine-stage PN code PN9, the digit number information is set to “000”.
By setting to “0”, only the shift register 101 generates the PN code. When generating 11-stage PN11, the shift register 101 is set with the digit number information as "0001".
And the shift register 102 to generate a PN code. Similarly, PN code PN15, PN code PN20, P
When generating the N code PN23, a predetermined PN code can be generated by setting the digit number information to “0011”, “0111”, and “1111”. In the decoder 30, as shown in the circuit diagram of FIG. 2, the AND of the coefficient input given to the input terminal 31 and the outputs of all the element registers from 1 to 23 is taken by the AND gate 32. The output of the AND gate 32 is an exclusive OR circuit 33
Through the output of the decoder 30. For example, the digit number information is “0000”, and the coefficient input is “000 0000 00”.
00 0000 0001 0001 ”, the outputs of the element registers 1 and 5 are input to the 2 → 1 selection circuit 201 via the decoder 30.
The shift register 701 and the exclusive OR circuit 801 in FIG.
This is equivalent to selecting a PN code generation circuit for the PN code PN9. PN code PN11, PN15, PN
Since the same applies to 20 and PN23, the description is omitted. Table 1 shows a set of digit number information and coefficient input when the same PN code as the conventional PN code generation circuit of FIG. 3 is generated.

[0009] Therefore, according to the configuration of the above-described embodiment, when a plurality of PN codes are generated, all of the predetermined PN codes can be generated using the number of shift registers equal to the maximum number of stages.

[0010]

As described above, the present invention has an effect that the number of shift registers for generating a PN code can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram according to an embodiment of the present invention;

FIG. 2 is a circuit connection diagram showing details of the decoder of FIG. 1;

FIG. 3 is a circuit configuration diagram showing a conventional PN code generation circuit.

[Explanation of symbols]

101, 102, 103, 104, 105 shift register, 201, 202, 203, 204 2 → 1 selection circuit, 30 decoder, 31 decoder input terminal, 32 decoder AND gate, 33 decoder exclusive OR circuit, 40 decoder Coefficient input terminal, 50 digit number information input terminal, 60 PN code output terminal.

Claims (1)

(57) [Claims] 1. A P which generates n different PN codes
In N code generating circuit, the number of stages of each of the PN code to be generated _{m i (i = 1,2, ...} , n; m i> m i-1; m
₀ = 0) to the time, a shift register is divided into n for each m _i -m _i-1 stage, is inputted from each of the parallel output and external m _n number of elements registers constituting the shift register A decoder for generating a signal to be serially input to the shift register from a coefficient input of a generator polynomial; and n-1 2 → 1 selection circuits, and the output of the decoder is n−1 2 → 1 Input to one input terminal of each of the selection circuits and the msb of the n-th shift register, and j (j = 1,..., N−1)
The lsb output of the (j + 1) th shift register is input to the other input terminal of each of the second 2 → 1 selection circuits, and the output of the jth 2 → 1 selection circuit is the jth shift register. A PN code generation circuit, which is connected so as to be input to msb of a register and controls the selection of the 2 → 1 selection circuit based on digit number information input from outside.