JPH0563522A - Pn code generating circuit - Google Patents

Abstract

PURPOSE:To reduce number of shift registers for generating plural kinds of PN codes by using dividedly one shift register whose stage length is equivalent to that required for generating PN codes of a maximum stage number indepen dently of kinds and numbers of PN codes. CONSTITUTION:2 1 Selection circuits 201-204 are switching circuits in which output 1sb of shift registers 102-105 when digit number information is logical 1 and output an output from a decoder 30 when the information is logical 0. Thus, a number of stages of the shift register required to generate PN codes is increased/decreased by setting how to give digit number information. Thus, in the case of generating 9-stages of PN codes PN9, '0000' is set to the digit number information to allow only the shift register 101 to generate PN codes. In the case of generating 11-stages of PN codes 11, '0001' is set to the digit number information and the shift registers 101, 102 are connected, Similarly, in the case of generating PN codes PN15, PN20, PN23, '0011', '0111', '1111' is set to the digit number information respectively to generate required PN codes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN code generation circuit for generating a plurality of types of PN codes and selectively outputting them.

[0002]

2. Description of the Related Art In a conventional PN code generation circuit, n types of P
When generating N codes, n shift register groups corresponding to the respective code types are used. FIG. 3 shows 5
It is a figure which shows the structure of the conventional PN code generation circuit which produces | generates the PN code of a kind. The first PN code (PN9 in this example)
Shift register 701 for generating a stage), an exclusive OR circuit 801, and a second PN code (P in this example).
Shift register 702 for generating N11 stages), an exclusive OR circuit 802, and a shift register 70 for generating a third PN code (PN15 stages in this example).
3, an exclusive OR circuit 803, a shift register 704 for generating a fourth PN code (PN20 stages in this example), an exclusive OR circuit 804, and a fifth P
A shift register 705 for generating an N code (23 stages of PN in this example), and a total of five shift register groups of an exclusive OR circuit 805 are provided, and these outputs are output from 5 → 1.
The PN code input to the selection circuit 90 and selected by the selection control signal input 70 input from the outside is output to the PN code output terminal 60.

[0003]

However, the above-mentioned conventional PN code generation circuit requires the same number of shift registers as the number of types of PN codes to be generated. Therefore, as the number of types of PN code increases, the number of shift registers also increases. There is a drawback that the number of circuits increases and the circuit scale increases.

The present invention solves such a conventional problem by dividing and using one shift register having a length corresponding to the generation of the maximum number of PN codes regardless of the number of types of PN codes. An object of the present invention is to provide a PN code generation circuit that can generate a plurality of types of PN codes.

[0005]

In order to achieve the above object, in the present invention, the number of stages of each PN code generated in a PN code generation circuit for generating n kinds of different PN codes is m _i ( i = 1, 2, ..., N; m _i > m
_i-1; when the m ₀ = _0), n for each m _i -m _i-1 stage
From the parallel register of each of the m _n element registers constituting the shift register and the coefficient input of the generator polynomial input from the outside,
The shift register includes a decoder that generates a signal to be serially input, and n-1 2 → 1 selection circuits, and the output of the decoder is one input of each of the n−1 2 → 1 selection circuits. Terminal and the msb of the n-th shift register, and the j + 1-th shift register is input to the other input terminal of each of the j (j = 1, ..., n-1) -th 2 → 1 selection circuit. Lsb output is input, and each output of the j-th 2 → 1 selection circuit is j
The second shift register is connected so as to be input to the msb of the shift register, and the 2
→ 1 Select circuit control.

[0006]

Since the present invention is constructed as described above, the PN code determined by the coefficient input can be generated by selecting the number of stages of the PN code to be generated by the digit number information.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram showing a configuration in one embodiment of the present invention when n = 5. A case where the same PN code as in FIG. 3 is generated will be described so as to facilitate comparison with the conventional example shown in FIG. That is, the number of stages of each generated PN code is m _i (i = 1, 2, ..., 5; m _i > m _i−1 ;
m ₀ = 0), m ₁ = 9, m ₂ = 11, m ₃ =
15, m ₄ = 20 and m ₅ = 23. 101,10
2,103,104, and 105, respectively m _i -
_i divided into 5 for each m _i-1 stage (i = 1, 2, ...,
5) The second shift register, and the number of stages of each shift register is m ₁ −m _O = 9 for the first and m ₂ −m _{1 for the second.}
2,3 th m ₃ -m ₂ = 4,4 th m ₄ -m ₃ =
5,5 th is m ₅ -m ₄ = 3. In the element registers of the shift register, 1 to 23 from lsb to msb in order.
The numbers up to are given. 201, 202, 203 and 204 are i-th (i = 1, 2, ..., 4) -th 2
→ 1 selection circuit, i + 1 shift registers 102, 103,
The lsb outputs of 104 and 105 are input, and the respective outputs are input to the msb of the i (i = 1, 2, ..., 4) th shift register 101, 102, 103 and 104. Reference numeral 30 denotes a decoder, which outputs the output of each element register j (j = 1, 2, ..., 23) and the coefficient input of the generator polynomial in parallel from the coefficient input terminal 40. The output of the decoder 30 is the 2 → 1 selection circuit 20.
The other input of each of 1, 202, 203, and 204 (upper side in the drawing) and the fifth shift register 105
Is input to the element register 23, which is the msb of. 2 → 1
The digit number information is input from the digit number information input terminal 50 to each control input of the selection circuits 201, 202, 203 and 204.

Next, the operation of the above embodiment will be described. 2 → 1 selection circuits 201, 202, 203 and 20
Reference numeral 4 denotes shift registers 102, 103, 104 and 105 when the digit number information which is a control input is "1".
Lsb is output and the output from the decoder 30 is output when it is "0". Therefore, the number of stages of the shift register necessary for generating the PN code can be adjusted depending on how the digit number information is given. .. Therefore, when generating a nine-stage PN code PN9, the digit number information is set to "000.
By setting it to "0", only the shift register 101 generates the PN code. When 11-stage PN11 is generated, the shift register 101 is set with the digit number information as "0001".
And the shift register 102 are connected to generate a PN code. Similarly, PN code PN15, PN code PN20, P
When the N code PN23 is generated, a predetermined PN code can be generated by setting the digit number information to "0011", "0111", and "1111", respectively. In the decoder 30, as shown in the circuit diagram of FIG. 2, a logical product of the coefficient input given to the input terminal 31 and the outputs of all the element registers 1 to 23 is taken by the AND gate 32. The output of the AND gate 32 is the exclusive OR circuit 33.
Through the output of the decoder 30. For example, the digit number information is "0000" and the coefficient input is "000 0000 00".
By setting "00 0000 0001 0001", the outputs of the element register 1 and the element register 5 are input to the 2 → 1 selection circuit 201 via the decoder 30,
The shift register 701 and the exclusive OR circuit 801 shown in FIG.
This is equivalent to selecting the PN code generation circuit for the PN code PN9 by and. PN code PN11, PN15, PN
Since the same applies to 20 and PN23, description thereof will be omitted. Table 1 shows a set of digit number information and coefficient input when the same PN code as the conventional PN code generation circuit of FIG. 3 is generated.

[0009] Therefore, according to the configuration of the above embodiment, when a plurality of PN codes are generated, it is possible to generate all the predetermined PN codes by using the number of shift registers equal to the maximum number of stages among them.

[0010]

As described above, the present invention has an effect that the number of shift registers for generating a PN code can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram according to an embodiment of the present invention,

2 is a circuit connection diagram showing details of the decoder shown in FIG. 1;

FIG. 3 is a circuit configuration diagram showing a conventional PN code generation circuit.

[Explanation of symbols]

101, 102, 103, 104, 105 shift register, 201, 202, 203, 204 2 → 1 selection circuit, 30 decoder, 31 decoder input terminal, 32 decoder AND gate, 33 decoder exclusive OR circuit, 40 Coefficient input terminal, 50 digit number information input terminal, 60 PN code output terminal.

Claims (1)

[Claims] 1. A P for generating n kinds of different PN codes.
In the N code generation circuit, the number of stages of each generated PN code is m _i (i = 1, 2, ..., N; m _i > m _i−1 ; m
₀ = 0) to the time, a shift register is divided into n for each m _i -m _i-1 stage, is inputted from each of the parallel output and external m _n number of elements registers constituting the shift register A decoder for generating a signal to be serially input to the shift register from a coefficient input of a generator polynomial and n-1 2 → 1 selection circuits are provided, and the output of the decoder is n−1 2 → 1. Input to one input terminal of each of the selection circuits and msb of the n-th shift register, and j (j = 1, ..., N-1)
The lsb output of the (j + 1) th shift register is input to the other input terminal of the 2nd → 1st selection circuit, and the output of the jth 2 → 1 selection circuit is the jth shift. A PN code generation circuit, which is connected so as to be input to msb of a register, and controls the selection of the 2 → 1 selection circuit according to digit number information input from the outside.