SU842787A1 - Device for scanning combinatorial samples - Google Patents

Description

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The invention relates to automation and computing and can be used to solve combinatorial problems, as well as to generate code sequences in control devices.

Combinatorial devices are known that enumerate permutations. One of the known devices contains ring registers, delay lines, threshold elements, a pulse generator, and a logic unit, which includes an adder, an implicator, and a waiting multivibrator. Such a combinatorial device provides 15 for the enumeration of all P permutations, but does not generate repetition permutations and arrangements 1. -

The closest to the proposed invention 20 is a combinatorial device containing n serially connected K-bit counters and a group of elements AND whose outputs are the outputs of the device and 25 devices are the input of the n-th counter. Such a combinatorial device ensures the sequential selection of C combinations for all values of n, starting from one. 2. 30

The drawback of the device is the impossibility of generating permutations with repetitions and arrangements.

The purpose of the invention is to expand the functionality by implementing permutations with repetitions.

The goal is achieved by the fact that a dispensing block is inserted into the device, the i-ro (i) outputs of the counter are connected to the inputs of the i-th group of the issuing permission block, each counter of the counter being connected to the first input of the corresponding I group, the second input of which connected to the output of the output permitting unit.

The issuing permission block contains (k-1) groups of elements AND, (e-1) of the input adders and element AND, with the inputs of each i-ro element AND j-I (k. 1) of the group connected to the inputs of the i-th group of the resolution block the outputs, and the outputs of the elements AND of the J-group are connected to the inputs of the j-rd adder, while the outputs of all the adders are connected to the inputs of the element I, the output of which is the output of the output permitter unit.

 the output resolution contains Cn, the comparison circuits and the OR-NOT element, and the inputs of the E th (i 1, cj) of the first and second groups of comparison circuits are the inputs of the S th (, n) and t th (t I, ,) the output resolution block groups, while S t and for any two circuits are compared pair S., t are not equal to each other, and the outputs of all comparison circuits are connected to the inputs of the OR-NOT element whose output is the output of the output resolution block . FIG. 1 shows a block diagram of a device for iterating over combinatorial samples; in fig. 2 is a functional diagram of an apparatus for generating permutations with repetitions of five elements (n 2, n, −1, n 2, n n 3 5) in FIG. 3 shows a functional diagram of the device for generating allocations of five elements of three (m 5, p 3); in fig. 4 variant of 5 input sum% 1ator. A device for sorting out combinatorial loops (Fig. 1) contains, n series-connected counters 1, a group of 2 elements I, an issuing permission block. The outputs of the elements And group 2 are the outputs of the device, and the input of the device is from the input of the nth counter 1. The outputs ir (i 1, n) of the counter 1 are connected to the inputs of the i-th group of the issuing permission block 3, each output of the counter 1 is connected to the first input of the corresponding element AND of the group, the second input of which is connected to the output of the issuance resolution unit 3. A device for generating permits with repetitions P (2, 2, 2) (Fig. 2) contains five counters 4-8, group 9 of elements I, block 10 of issuing permission, composed of group 11 of elements 11 and 12 16, a group of 17 elements And 18-22, two 5-input adders 23 and 24, element And 25. The conversion factors for all counters are 3. The output of each subsequent counter is connected to the previous input, and the input of the last counter is connected to the clock bus 26. Each counter output is connected to the first input of the corresponding element AND of group 9, the second input of which is connected to the output of the dispensing resolution unit 10. (The meters 4 are connected to the inputs of the elements And 12 of group 11, And 18 rpyiifM 17. The outputs of the counter 5 are connected to the inputs of the elements And 13 of group 11, And 19 of the group 17. The outputs of the counter 6 are connected to the inputs of the elements And 14 of group 11 , and 20 groups 17. The outputs of the counter 7 are connected to the inputs of elements 15 of group 11, and 21 of group 17. The meters of the counter, 8 are connected to the inputs of elements 16 of group 11, and 22 of group 17. One of the possible options for building a 5-input adder shown in Fig. 4. The adder contains two one-digit adders 27 and 28 for two inputs, two one-digit adders 29 and 30 to three inputs. The outputs of the elements And 12-16 groups. 11 are connected to the inputs of the 5-input adder 23. The outputs of the elements And 1822 of group 17 are connected to the inputs of the 5-input adder 24. The outputs of the adders 23 and 24 are connected to the inputs of the element And 25 The output of which is the output of resolution unit 10, the issuance. The device for generating arrangements A 5 (FIG. 3) contains three counters 31-33, a group of 34 elements And, block 35 of issuing permission, which includes three comparisons 36- 38, element OR-NOT 39. One of the possible options for building a comparison scheme is en on fig.Z. The coefficients for recalculating the equality of the codes of all counters are 5. The output of each subsequent counter is connected to the input of the previous one, and the input of the last counter is connected to the clock pulse bus 40. Each output of the counter is connected to the first input of the corresponding element And group 34, the second input which is connected to the output of the issuance permit block 35. The outputs of the counter 31 are connected to the first group of inputs 36 and 37 of the comparison circuits. The outputs of the counter 32 are connected to the second group of inputs 36. comparison circuit and connected to the first group of inputs 38 of the comparison circuit. The outputs of the counter 33 are connected to the second group of inputs 37 and 38 of the comparison circuit. The outputs 36-38 of the comparison circuit are connected to the inputs of the element OR-HE 39, the output of which is the output of the issue permitting unit 35. In the mode of generating permutations with repetitions, the device operates as follows (Fig. 2). The output of the 5-input adder receives a binary code of the number of inputs to which single signals have arrived. The first clock pulse arrives at the input 8 of the counter from the bus 26 and sets the counters 4, 5, 6, 7, and 8 respectively to 1.2 and 2. At the outputs of the high and low bits of counters 4,5,6 , 7 and 8, respectively, signals 00,00,01,10 and 10 arrive. Zero signals from the outputs of counters 4 and 5 are fed to the inverse inputs of the And 12, And 13 elements, respectively, the single signals from the outputs of which go to the first and second inputs of the adder 23 The single signal from the low-bit output of counter 6 closes the element And 14. The single

the signals from the outputs of the higher bits of the counters 7 and 8 of the closing signals respectively the elements 15 and 16. The zero signals from the outputs of the elements 14 and 15, and 16 are fed to the third, fourth and fifth inputs of the adder 23. From the outputs of the adder

23 signals 0.1 and O are fed to the inputs of the element And 25.

Zero signals from the low-order outputs of counters 4, 5, 7 and 8 are covered by elements 18 and 19, 21 and 22, respectively, and zero signals from the outputs of which output the first / second, fourth and fifth inputs of the adder 24. Zero signal from the output of the high bit of the counter 6 opens element I 20, through which a single signal from the output of the low bit of counter 6 passes to the third input of the adder 24, From the outputs of the adder 24, signals 1, O and O arrive at the inputs of the element I 25,

A single signal from the output of the AND 25 element opens AND elements of group 9 and permits the issuance of state codes of counters 4-8. Thus, the first cycle of operation implements the first permutation with repeats 00122, where the position numbers of the digits in the permutation correspond to the counter numbers, and the digits at these positions correspond to the decimal notation of the binary codes of the states of the counters.

The second clock pulse arrives at the input of the counter 8 from the bus 26 and sets the counters 4-8 respectively to the state 0,0,2,0 and О, the outputs of the counters 4-8 receive the signals 00,00,10,00 and 00 respectively .

Zero signals. The outputs of the lower bits of counters 4-8 are covered by elements AND 18-22, respectively, the zero signals from the outputs of which arrive at all inputs of the adder24. Zero signals from the outputs of the adder

24 closes the element And 25, the zero signal from the output of which prohibits the issuance of status codes of counters 4-8.

The third clock pulse arrives at the input 8 of the counter from the bus 26 and sets the counters 4-8, respectively, to the state 0,0,2,0 and 1,

The outputs of the counters 4-8 receive signals 00,00,10,00 and 01, respectively,

Zero signals from outputs 4.5 and counters arrive at the inverse inputs of the And 12 And 13, And 15 elements, respectively, single signals from the outputs of which go to the first, second and fourth inputs of the adder 23, Signals 1.1 and Oct of the outputs of the SumMmator 23 close the element And 25, the zero signal from the output of which zap5 "ztats the issuance of state codes of counters 4-8,

On the Drive of the counter 8 from the bus 26 enters the seventh clock pulse. The outputs of the counters 4-8 receive signals 00,00,10,01,01 and 10, respectively. Zero signals from the outputs of counters 4 and 5 are fed to the inverse inputs of the And 12, And 13 elements, respectively, the single signals from the outputs of which go to the first and second inputs adder 23.

From the outputs of the adder 23 signals

0 0,1 and About arrive at the inputs of the element And 25,

A zero signal from the output of the high bit of counter 7 opens element I 21, through which a single signal from the output of the low bit of counter 7

5 passes to the fourth input of the adder 24, From the outputs of the adder 24, the signals 1.0 and O are fed to the inputs of the element And 25.

A single signal from the output of the AND 25 element opens AND elements of group 9 and permits the issuance of state codes of counters 4-8. Thus, the second permutation with repeats 00212 is realized on the seventh cycle of operation.

five

The operation of the device is illustrated in table. 1, in which the states of counters 4–8 are presented. Those cycles in which the device generates permutations from another and P (2, 1, 2) are numbered.

At the last operation cycle of the device, a thirtieth permutation with repetitions of 22100 is realized,

In the mode of generating allocations, the device operates as follows (5, FIG. 3),

The output of the equality circuit receives a single signal in the case of equality of codes arriving at the inputs of the equality circuit of the first and second groups.

0

The first clock pulse arrives at the input of the counter 33 of the region 40 and sets the counters 31-33 to the state of 0.1 and 2, respectively. At the high, middle and junior bits

5 counters 31-33 receive signals 000, 001 and 010 respectively,

From the outputs of the counters 31 and 32, signals 000 and 001 come to the first and second groups of inputs of the comparison circuit 36, respectively. From the outputs of the counters 31 and 33 of the signals 000 and 010, go to the first and second groups of inputs of the comparison circuit 37, respectively. From the outputs of the counters 32 and 33-signals 001 and 010, respectively, go to the first and second groups of inputs. Comparison circuits 38, Zero-signals from the outputs of the comparison circuits 36-38 go to the inputs of the OR-NOT 39 element, the single signal from the output whom

0 opens the AND elements of group 34- and allows the issuance of status codes of counters 31-33,

Thus, on the first tact of work the first placement is realized

5 012, where the position numbers of the digits in the arrangement correspond to the numbers of the counters, and the digits / figures on these positions correspond to the decimal notation of the binary codes of the counters. The second clock pulse arrives at the input 33 of the counter from the bus 40 and sets the counters 31-33 to the 0.1 and 2, respectively. The signals of 0.00, 001 arrive at the output of the higher, middle, and lower digits of the counters 31-33, respectively. and 011, From the outputs of the counters 31 and 32, signals 000 and 001, respectively, arrive at the first and second groups of inputs of the equality circuit of codes 26. From the outputs of the counters 31 and 33, signals 000 and 011 go to the first and second groups of inputs of the comparison circuit 13, respectively; From the outputs of counters 32 and 33, signals 001 and 011 are fed to the first and second groups of inputs of the comparison circuit 38, respectively. Zero signals from the outputs of the comparison circuits 36-38 arrive at the inputs of the OR-NOT 39 element, a single signal from the output of which opens the AND elements of the group 34 and allows the issuance of state codes of the counters 31-33. Thus, in the second cycle of operation, the second placement 013 is realized. The fourth clock pulse arrives at the input of the counter 33 from the bus 40 and sets the counters 31-33 respectively to the state of 0.2 and 0. The outputs of the higher, middle, and lower bits of the counters 31-33, signals 000, 010 and 000, respectively, arrive. From the outputs of the counters 31 and 32, signals 000 and 010, respectively, arrive at the first and second groups of inputs of the comparison circuit 36. The G outputs of the counters 31 and 33, the signals 000 and 000, arrive respectively at the first and second groups of inputs of the Schecel 37 comparison. From the outputs of the counters 32 and 33, the signals 010 and 000 go to the first and second groups of inputs of the comparison circuit 38, respectively. From the outputs of the comparison circuits 36-38, the signals 0.1 and O are fed to the inputs of the element OR-NOT 39, the zero signal from the output of which closes the AND elements of group 34 and prohibits the issuance of status codes of counters 31-33. The operation of the device is illustrated in table. 2, in which the states of the counters 31-33 are presented. The cycles in which the device generates placements A are numbered. At the last cycle of operation of the device, the sixty placement 432 is realized. The known device provides a sequential search for the combination C with all values of n, starting from one. In comparison with this, the proposed device expands its functional capabilities, due to the implementation of all P (n, n,.,., ,,,), permutations with repetitions of state codes n + n 2. .. + n at counters with conversion factors equal to k, of all A placements of state codes n counters with coefficients peresta, equal to m. In case of equality of the coefficient, recalculation to (or ha) the number of counters) n, the proposed device implements all nf permutations of state code counters. The invention can be used to solve combinatorial problems (enumeration of polynomial coefficients, calculation of permanents), as well as problems of computational mathematics (disclosure of determinants of matrices). These tasks are not known to solve the device. An implementation of the invention is proposed. neither in the production at ELECTRONNASH, as well as in the data processing system developed by the department of computer technology together with the SCR MMS IC of the Ukrainian Academy of Sciences.

Permutations with repetitions

i: f :: i: i: r :: f :::: j: i: L: i :: :::: i

Table

Claims (3)

Continued table. 1 Claim 1. A device for iterating over combinatorial samples, containing n series-connected k-bit counters and a group of elements AND, whose outputs are the device's outputs, and the device's input is the input of the n-th counter, differently that, in order to extend the functionality due to the implementation of all permutations with repetitions and all layouts, the device contains an issuing permission block, with the i-ro (, ... n) outputs of the counter being connected to the inputs of the i-th group of the issuing permission block, with each the output of the counter is connected to the first input of the corresponding Element And groupgill, the second input of which is connected to the output of the output permitting unit. 2. The device according to claim 1, that is, so that the issuing permission block contains (k-1) groups of elements I, (k-1) n-input adders and element I, and the inputs each i-ro element AND j-th (, k-1) of the group are connected to the inputs of the i-th group of the issuance resolution block, and the outputs A continuation of the table, 2 elements of the j-th group are connected to the inputs of the j-ro adder, while the outputs of all adders are connected to the inputs of the element I, the output of which is the output of the output resolution block, 3. The device is pop, 1, characterized in that the resolution block is C of the comparison circuits and the element OR NOT, and the inputs of the 8th (C, the comparison circuit of the first and second groups are the inputs respectively (Sl, .njl and t th (t 1, n) groups of the output resolution block, with S t and for any two comparison circuits of the pair S, t are not equal to each other, and the outputs of all comparison circuits are connected to the inputs of the OR-NOT element whose output is the output issuance permitting unit. Sources of information attached to consideration during the examination 1. USSR author's certificate No. 446057, class G About F 1 5/20, 1974. 2. Certificate of CCCI No. 374606, class G 06 F 15/20, 1973 (prototype). A / /. V / /  i five u / f I / 2J .J - 2f iJL L. LIL I 2