SU903891A1 - Device for scanning combinations - Google Patents

Description

(64) DEVICE FOR COUNTING COMBINATIONS

one

This invention relates to a calculator. technology and can be applied, nahfimer, in computers that solve combinatorial problems.

A device for enumerating combinations is known, comprising a main register, an EEShomination register, an auxiliary register, a skip block, triggers, AND and OR elements, SI delay elements.

A disadvantage of the known device is that it contains a large number of elements, which reduces the reliability of operation.

The closest technically to the invention is a device for sorting combinations of elements by, and containing shift registers, a counter, a trigger, a trigger, AND elements, delay elements, 15) a pulse divider, the first output of which is connected to the first input of the first shift register, the second input is with the first input of the first element I, the second input of which is connected to the control bus, the output

The first element And is connected to the second input of the shift register and through series-connected counter and the first delay element connected to the zero input of the trigger, the first, second and third inputs of the second shift register are connected respectively to the first and second outputs of the decoder and the output of the first delay element shear connected to the first input

10 of the first shift register and the device output, the first output of the first shift register is connected to the first input of the second element, the third input of the first shift register is connected to the output of the second delay element, the first output of the first shift register is connected to the first; the input of the second element And, the second input of which is connected to the zero output of the trigger, the output of the element And

30, the second delay element is connected to a single trigger input, the zero input of which is connected to the first input of the decoder, the second input of which is connected to the second input of the second And element, the third input of the decoder is connected to the third input of the first shift register, the fourth input of the decoder is connected to the output of the first element And, 2. A disadvantage of this device is its complexity, due to the presence of two shift registers, a decoder, a counter (recalculation coefficient vn), a pulse distributor, made in the form of a shift register. As a result, the device has a low speed and low adaptability to circuit changes when changing the value of VV1. The purpose of the invention is to simplify the device. The delivered chain is achieved by the fact that the device for searching combinations, containing an m-bit register, a group of (t-2) delay elements, an And element and a trigger, the zero output of which is connected to the first input of the And element, contains the first group of {vn - 1) elements And, the second group of elements And, the third group of (mi) elements And, the fourth group of (w, - 2) elements And, the first group of (wi -l) elements OR, the second group of (il 2) elements OR, and the device input is connected to the first input of the first element AND of the second group, to the first input p of the third element And the third group and to the zero input of the trigger, a single input of which is connected to the output 35 of the element And, the second input of which is connected to the output of the first element OR of the second group and to the first input of the first element And the fourth group, the second input of which is connected to the single output trigger, the second input of the gth element AND the second group (i 1, 2, ..., v,) is connected to the unit output of the i-th digit of the register and to the first input of the j-th element of the fourth group (j 2, 3 "-2), the output of the t-th element And the second group () is connected to the first inputs -X elements AND and OR of the first groups, respectively (i 1, 2,.,., s1), the second input of the i-th element OR. 50 of the first group is connected to the output of the t-th element of the third group and to the first input of the (. + 1) -th element of the third group, the second input of the i-th element of the third group is connected to the zero 55 output of the i-th bit of the register, respectively which is geo-connected to the second input of the го element of the first group, 4. the output of which is connected to the first single input of the register bit, the second. whose single input is connected to the output of the j-th element of the fourth group and to the second input (j + 1) of the element AND of the fourth group, zero input of the i-th register bit (iw) is connected to the output of the i -th element of the second group and to the first input of the j-th element OR of the second group, the second input of the kotor, is connected to the output of the -th delay element of the group whose input is connected to the output j (j tn-З) of the element OR of the second group, the output -ro of the element AND of the second group is connected to the output of the end of the enumeration of device combinations and to the zero input of the kth register bit, stroke (the "2) th delay element group is connected to the zero input (yy - 1) -th register. The drawing shows a diagram of the device. The device contains a register formed by triggers 1, and a pulse distributor formed by AND 2 elements, AND 3 elements, OR 4 elements, AND 5 elements, AND 6 elements, delay element jj 7, OR 8 elements, trigger 9, AND 1O element, bus Ts input pulse, bus 12 signal of the end of the search. When combining combinations, each successive state is formed from the previous ™ At the replacement of the rightmost combi “« Ю Ol on U and the census of all units to the right, to the edge of the “прав right positions. In this case, in the initial state all units should be located in the extreme right positions, while in the last state they move to the extreme left positions. For example, with S and 3, the device produces OOI11 combinations. Before starting work, to iterate over all combinations of wi elements, all triggers of 1 register are set to the zero state, and then the units are written in v rightmost triggers i and 1, 2. ., silt - 1). Each time the input pulse arrives on the bus Q, the trigger 9 raspedelitel pulses is set to the zero state, ensuring that. the most resolving potential at the control input of the element And 10 and the inhibiting potential at the control input of the first element And 6 of the fourth group. The same pulse arrives at the information inputs of the first element And 3 of the second group and the first element And 5 of the third group. In the case of the unit state of the 1st register triggers, the control potentials of the control inputs of the And 3 and 6 elements of the second and fourth groups are resolving potentials, the control inputs of the And 2 and And 5 elements of the inhibitory potentials, on the contrary, the triggers 1 of the register the control inputs of the elements And 3 and And 6 are the inhibitory potentials, and at the control inputs of the elements And 2 and And 5 are the enabling ones. If y (Γ i, 2, ..., y) rightmost triggers 1 are in one state, then the input pulse passes successively elements And 3 of the second group and OR 4 of the first group and sets these triggers to zero state, and the (and +1) th trigger 1 through the open element AND 2 of the first group is in one state and, moreover, is supplied to the inputs of the elements OR 8 of the second group, which ensures the formation of the series from the output of the first element OR 8 of the second group 1 pulses (delay elements 7 provide a temporary stretch of a series of pulses, it is necessary th for transient stability in future work). The first impulse of the series, having passed through the element 10, sets the trigger 9 of the pulse distributor into the unit state, thus providing the first input element 6 and the fourth group of the resolving potential to the control input. The second impulse of the series, having passed the first element AND 6 of the fourth group, sets the first trigger, 1 register to the one state, which ensures the passage of the third pulse of the series through the second element 6 of the fourth group and setting the 1 trigger of the first register to 1, and with each the next pulse of the series is the installation of the next in order trigger 1 register inclusive (ir - l) -th trigger. This completes the tact of forming the next combination, which is removed from the single inputs (a, a, and O-rv, register 11 triggers.). If 1 (1,2, ..., mi) the rightmost triggers of 1. ts in the zero state, the input impulse, passed t of the open elements AND 5 of the third group, goes through the gth element OR 4 of the first group to the open I G + 1) -th element AND 3 of the second group and then performs the actions similar to those described. If in the current combination there is an O1 combination in the extreme right position, then when forming the next combination, it is converted into combination 10, which corresponds to a unit shift by one bit to the left. If the leftmost flip-flops 1 of the register are in the single state {the last of the generated combinations), then when the next input pulse arrives from the output of the last element And 3 of the second group, the end of brute-force signal is output via bus 12. The technical and economic effect of using this device is to simplify the technical implementation of the device and increase its reliability by reducing the number of elements (about 30%), as well as improving its speed by eliminating shift registers and the need to rewrite the codes from the register to the register. In addition, the device design can be represented as tn cells connected in series, each of which contains a trigger 1, four AND elements (2.3.5 and 6), two OR elements (4 and 8) and one delay element 7. Such a construction provides the simplicity of the circuit change of the device — with an increase (decrease) in the value of y, the corresponding number of cells is included (excluded) in the device. Claims of the invention A device for sorting combinations containing a vvi-bit register, a group of (K1 - 2) delay elements, an And element and a trigger, the zero output of which is connected to the first input of the AND element, characterized in that, in order to simplify the device, it contains the first group of (VM -l) elements And, the second group of elements And, the third group of (m - l) elements And, the fourth group of (i -2) elements And / the first group of (um - 1) elements OR, the second .group of lw 2) elements OR, by the input of the device is connected to the first input of the first ele cient and second group, the first .k; the input of the first element And the third group n to the zero input of the trigger, a single input of which is connected to the output of the element AND, the second input of which is connected to the output of the first element OR of the second group and to the first input of the first element AND of the fourth group, the second input of which is connected to the single output of the trigger , the second input of the i-th element of the second group (4. 1, 2, ..., I) is connected to the single output H – gr of the register register and to the first. the entry of the th element And the fourth rpyi p V 2, 3, ..., and -t 2) ,. output of the i -th element AND of the second group () is connected to the first inputs of the I -k elements AND and OR of the first groups, respectively (I 3 ,, 2, ..., yn-l), BtqpoS input of the -th element OR of the first group connected to the output of the th element of the third group and to the first input (-C + fi) -ro of the element AND of the third group, the second input of the i-th element of the third group is connected to the zero output of the t-th digit of the register, respectively, 9 91 which is connected to the second input of the AND element of the first group, the output of which is connected to the first single input of the register bit, the second single input of which oh connected to the output of the j-th element of the fourth group and to the second input I j + 1) of the element of the fourth group, the zero input of the i-th register (t h n) is connected to the output of the t th element of the second group in the first input J the element OR the second group:, the second input of which is connected to the output of the th element of the delay group, the input of which is connected to the output j + l-ro (Pack -3) of the element OR of the second group, the output of the -th element AND of the second group is connected to the output of the end of brute force combinations of the device and to the zero input of the w-th branch of the register, the input of the (w - 2) -th element group delay is connected to the zero input (w - I) -th register. Sources of information taken into account in the examination 1. USSR author's certificate number 514295. cl. G About F 15 / 2O, 1973. 2. USSR author's certificate No. 634285, cl. (3 06 F 15/32, 1974 (prototype).

Claims (1)

Claim A device for sorting combinations containing an -bit register, a group of (m _ 2) delay elements, an element * and a trigger, the zero output of which is connected to the first input of the element And, characterized in that, in order to simplify the device, it contains the first a group of (g -1) elements And, a second group of elements And, a third group of (m - 1) elements And, a fourth group of (w -2) Ί 9 AND elements / the first group of (m - 1) · OR elements, the second group of I or 2) OR elements, by grill the device input is connected to the first input of the first AND element of the second group, to the first: the input of the first AND element of the third group and to the zero input of the trigger, unit-. whose 'input' is connected to the output of the AND element, the second input of which is connected to the output of the first OR element of the second group and to the first input of the first AND element of the fourth group, the second input of which is connected to the single output of the trigger, the second input of the i-th__ element AND the second group (4 = 1,2, · ”, 15 M) is connected to a single output 4th category register and 'to the first. the input of the jth element AND of the fourth group IJ = 2, 3, ..., s 2). I-th element output and the second group (ίφ ™) sub ₂ of the keys to the first inputs of the elements Z -x -. Comrade AND and OR of the first groups, respectively (I = 1, 2, ..., il - 1), the second input The Zth OR element of the first group is connected to the output of the £th element AND 25 of the third group and to the first input (4 + + i) -ro of the And element of the third group, the second input of the -th element AND of the third group is connected to the zero output i - the first digit of the register, respectively, 391 8 'which is connected to the second input of the Zth element AND of the first group, the output of which is connected to the first single, a register discharge input, the second single input of which is connected to the output of the jth element And the fourth group and to the second input I j +1) of AND element of the fourth group, the zero input of the t-th digit of the register (t h ¹ ® and ") is connected to the output of the 4" element AND of the second group and to the first input of the J-th element OR of the second group, the second input of which is connected to the output J - th element of the delay group. the input of which is connected to the output j + ♦ of the 1st (j - З) element OR of the second group, the output of the th element AND of the second group is connected to the output of the end of enumeration of combinations of the device and to the zero input of the νηth form of the register. - 2) of the group delay element is connected to the zero input (s - 1) of the register bit.