SU1241232A2 - Device for counting number of zeroes in binary code - Google Patents

Abstract

The invention relates to computing, automation, telemechanics and can be used to process binary codes of signals and is an improvement of the known device according to A.S. No. 1019440. The purpose of the invention is to expand the use of the device by implementing the code number selection procedure containing the greatest the number of zeros in the array of t-bit codes. To achieve the delivered circuit, a delay node, an AND element, an OR element, a group of comparison nodes, two groups of AND elements and two groups of triggers are additionally introduced into the device. 2 hp f-ly, 3 ill. (Ls

Description

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The invention relates to computing, automation and telemechanics, can be used for processing binary codes of signals and is an improvement of the known device according to author. W 1019440.

The purpose of the invention is to expand the scope of the device by implementing the operation of selecting the code of the number containing the largest number of zeros in the array of t-bit codes.

FIG. 1 shows a block diagram of a device for counting the number of zeros in a binary code; in fig. 2 - the functional diagram of the comparison node; in fig. 3 - functional delay node circuit.

The device for counting the number of zeros in a binary code contains a group of trigger I, groups of elements AND 2 and 3, elements AND 4 and 5, a group of elements OR 6, element 7 of delay, counter 8, trigger 9, groups of elements And 10 and 11 , element OR 12, group of comparison nodes 13, node 14 delays, trigger groups 1.5 and 16, element 17, numeric input 18 and clock input 19..

Each group comparison node has inputs 20-24, as well as output 25. Delay node 14 contains inputs 26 and 27, as well as output 28.

Each comparison node consists of AND elements 29-31, AND-NE element 32 and trigger 33.

The delay node is made in the form of the element And 34, the element 35 of the delay and the trigger 36.

A device for counting the number of zeros in a binary code works as follows.

In the initial state, the triggers of 1, 15, and 16 groups, as well as trigger 9 and counter 8, are in the zero state of the scientific research institute. Suppose you need to find a number containing the maximum number of zeros in an array of .N t-bit words. The binary code of the first number arrives from input 18 through a group of elements OR 6 to the input of a group of flip-flops 1, sets them to the corresponding bits in 1. After that, the clock pulses are fed to input 19 and far to the inputs of elements And 2 and 3 groups the sequential addition of the recorded in the triggers of the 1 group code to a single. These same pulses through

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delay element 7 and element 4 pass to the input of counter 8. At the moment when a single code is formed in group 1 triggers, all elements 3 are open and the clock signal arriving at single input of trigger 9 sets it to one. This leads to the cessation of the supply of pulses to the input of counter 8. Simultaneously, the AND element opens for the passage of clock pulses to the delay node 14 and overwrites the index counter 8 to the triggers of 15 or 16 groups according to which And element (10 or 11) groups is open. After that, the installation input triggers group 1, the trigger 9 and the counter 8 are transferred to the zero state. Thus, the device for counting the number of zeros is ready to receive the second m-bit word from the array, etc. Consider the process of comparing two codes of numbers in the device. At the initial moment, the group of elements AND 3 is closed by the inputs 22. As a result, the group triggers 33 are also in the zero state. At the output of the AND-NE elements 32 there are high potentials, since the first input of each AND-NE element 32 from the input 20 low potential comes from the direct output of the trigger 15 of the group, and the second input of the AND-32 element from input 23 receives a high potential from the inverse output of the trigger 16 of the group. When a clock pulse appears at the input of the first-bit comparison node, it arrives at the first input of the AND 30 element, as well as at the first input of the AND 29 element of the first discharge. Element I 30 is closed, since a low potential level is supplied to its second input from the direct output of trigger 33. Therefore, the clock pulse passed through the element

And 29 is the first discharge, open high potential with inverse

the output of the trigger 33, arrives in the second bit at the input of the element I 30, as well as at the first input of the element And 29. Similarly, the clock pulse is fed to the input of the node 13 comparing the third bit, etc. For the last tth bit, the clock pulse goes to the nth input (t + 1) of the input element I 29 ,. closed low potential with direct trigger output 33.

At the same time, the clock pulse is lowered to the input 26 of the delay node 24, sets the trigger 36 to the zero state and passes to the input of the delay element 34. After a delay

T (m + l) t ,,

where the delay time of the electric pulse in the AND / OR elements,

the impulse passed through the open high potential from the inverted output of the trigger 36 element 34 and arrives at the output 28 of the node 4 delays. Thus, the elements of group 11 are prepared to receive information from counter 8. Thus, the next word recorded in counter 8, - blunt in triggers 16 to the place of the previous one.

Suppose that this word has a unit, in the second category, i.e. the word written in the flip-flops 16 is more than the word stored in the flip-flops 15. In this case, the comparison of the first bits is made similarly to that considered. At node 13 of the second-bit comparison, the element I 31 is opened by applying to its inputs high potential levels from the inverse output of the trigger 15 and from the direct output of the trigger 16. The trigger 33 is set to a single state. A clock pulse from the output of element AND 29 of node 13 of the first-bit comparison passes through element AND 29, since the other inputs have high potential levels from the output of trigger 33 and from the output of AND-HE 32 nodes of the first discharge. Passing through the Hltli element 12, a clock pulse at the input 27 of the delay node 4 sets the trigger 35 to one state. At the same time, the clock pulse rewrites the information from the output of the counter 8 through the elements AND 10 groups into the triggers of the 15th group. Thus, as a result of comparing the two codes of numbers on the flip-flops 16, a larger number remains.

As a result of the operation of the proposed device, on the trigger 15 (16) of the second (third) group, the number corresponding to the largest number of zeros of the number is stored in the array N of n-bit words.

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232 Formula of Invention

Claims (3)

1. Device for counting the number of zeros in a binary code according to auth.St. No. 1019440, characterized in that, in order to expand the field of application of the device by implementing the operation of selecting the code of a number containing the largest number of zeros in the array of t-bit codes, it further comprises a delay node, a third AND element, an OR element, a group of comparison nodes, the third and fourth groups of elements are And, the second and third groups of triggers, the outputs of the elements And the third and fourth groups are connected to individual inputs of the corresponding triggers of the second and third groups, respectively, the first inputs of the elements And the third group is connected to the output of the OR element, the first inputs of the AND elements of the fourth group are connected to the output of the delay unit, the second inputs of the AND elements of the third and fourth groups are connected to the outputs of the corresponding counter bits, and the third inputs of the third and fourth groups are connected to the output of the first element And with the first input of the element And, the second input of which is connected to the clock bus of the device, and the input is connected to the first input of the delay node and to the first control input of the first node of the group comparison, the second input of the node and the delays are connected to the output of element 1-1) III, whose inputs are connected to the outputs of the smaller value of the corresponding group comparison nodes, the output is less than or equal to the value of each i-ro comparison node of the group, where, ..., (t-1), with the first control input of the (i + 1) -th comparison node of the group, the control inputs from the second to the jth, where, ..., m, of each j -th group comparison node, are connected to the outputs of a larger value of nodes comparison from the first to (-1) -th group, information inputs of the first node of the comparison group are connected respectively to the direct inputs of the first triggers of the second and third groups, information inputs of the remaining nodes of the comparison group connected respectively with direct and inverse outputs of the corresponding triggers of the second group and with direct and inverse outputs of the corresponding triggers of the third group. 2. A device according to claim 1, characterized in that each comparison node comprises three AND elements, an AND-NOT element and a trigger, wherein the first input of the first AND element is connected to the direct output of the trigger, and the remaining inputs are connected to the corresponding control inputs of the node , the output of the first element I is connected to the output of a smaller node value, the first input of the second element I is connected to the inverse output of the trigger, and the second input of the city to the first control input of the node, the output of the second element I is connected to the output of a smaller or equal node value, singlethe trigger input is connected to the output of the third element AND, the inputs of which are connected to the second and third inputs of the node, the first and fourth inputs of which are connected to the inputs of the NAND element, the output of which is connected to the output of a larger node value. 3. The device according to claim 1, about tl and - the fact that the delay node contains a trigger element And and a delay element, the first input of the delay node being connected to the input of the delay element and with a zero trigger input, the single input of which is. go is connected to the second input of the node delays, and the inverse output is connected to the first input of the And element, the second input of which is connected to the output of the delay element, the output of the And element is connected to the output of the delay node. 35 -n 27 26 fig.Z Editor A. Ogar Compiled by A. Stepanov Tekhred O. Gortvay Order 3490/44 Edition 671Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 FIG. 2 J " -025 J Proofreader L. Pilipenko