KR100247925B1 - Multiflier and operating method thereof - Google Patents

Abstract

A multiplier and method of operation thereof are disclosed. The multiplier multiplying the first data of M bits and the second data of N bits comprises: a first register for latching the first data in parallel, the bit generating means for generating the extension bits, the extension bits, and the first data; Parallel and serial conversion means for inputting the first data output from the register in parallel and sequentially outputting the serial data in response to the output control signal, a second register for inputting and latching the second data in parallel, and the parallel and serial conversion means. A first shifting means for outputting N-bit shifting data shifted in serial output in parallel, an AND operation means for ANDing the shifting data and the second data latched in the second register, and the output and carry data of the AND function Adding means for adding and outputting the added result, a third register for latching bits other than the least significant bit of the added result as carry data, and the least significant ratio of the added result. And a fourth register for latching the second register, a second shifting means for shifting the output of the fourth register, a fifth register for latching the output of the second shifting means in parallel and latching the result of the multiplication of the first data and the second data; A control means for generating an output control signal and generating a reset signal before the next multiplication operation is characterized in that it is inexpensive and reduced in size, which is advantageous in implementing an integrated circuit.

Description

Multiplier and its operation method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multipliers that can be implemented in integrated circuits, and more particularly, to low cost, small multipliers and methods of operation thereof.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of a conventional multiplier will be described as follows.

1 is a block diagram of a conventional multiplier, which is composed of first and second registers 10 and 12 and a multiplier 14.

The multiplier 14 shown in FIG. 1 inputs data X and Y having N bits in parallel and in parallel through the first and second registers 10 and 12, and inputs the input data X and Y to each other. Perform a multiplication operation. At this time, the structure inside the multiplier 14 is designed to add the values while shifting the bits.

The above-described conventional multiplier has a simple structure and a fast calculation result, but has a large size and a high price, so it is not suitable for use in actual integrated circuit implementation.

Instead of the multiplier 14 illustrated in FIG. 1, the multiplier may be operated using only a shifter and an adder. While the size of the scheme is smaller than that of the multiplier, the size of the shifter and the adder increases when the number of bits of the input data increases, which is advantageous over the multiplier illustrated in FIG. 1, but still has a small size.

An object of the present invention is to provide a low cost and miniaturized multiplier using a series adder and a shifter.

Another object of the present invention is to provide a multiplication method performed in the multiplier.

1 is a block diagram of a conventional multiplier.

2 is a block diagram of a multiplier according to the present invention.

In order to achieve the above object, in the present invention, the first data of M (where M is at least one positive integer) bits and the second data of N bits (where N is at least one positive integer) bits are multiplied. The multiplier includes: a first register for inputting and latching the first data in parallel, bit generation means for generating extension bits for expanding the most significant bit of the first data, and the extension bit and the first register. Parallel serial conversion means for inputting the first data output in parallel and sequentially outputting the input bits in series in response to an output control signal, a second register for inputting and latching the second data in parallel; First shifting means reset in response to a reset signal and outputting N-bit shifting data in parallel shifted from the serial output of the parallel-to-serial conversion means; N logical multiplication means for ANDing the second data latched in the second register, adding means for adding the output and carry data of the N logical multiplication means, and outputting the added result, and the added result. A third register for latching bits except the least significant bit of as the carry data, a fourth register for latching the least significant bit of the added result, a reset in response to the reset signal, and shifting the output of the fourth register Inputting the second shifting means and the output of the second shifting means in parallel to generate a fifth register and the output control signal latched as a multiplication result of the first data and the second data, and before the next multiplication operation. And control means for generating the reset signal.

In order to achieve the above another object, in a multiplier that multiplies the first data of M bits, where M is a positive integer of at least one positive integer, and the second data of N bits, where N is a positive integer of at least one positive integer. The multiplication method according to the present invention is performed by mixing the first data and the extension bits for expanding the most significant bit of the first data, the step of converting the mixed parallel data into serial data, and the serial Shifting the data into N bits of parallel data, logically multiplying the N bits of parallel data with the second data, adding carry data and the logical result of the previously added result; Shifting the least significant bit of the added result bits, latching bits other than the least significant bit as the carry data and the shifted least significant ratio That as a result of multiplication of the second data with the first data comprising the steps of: latching in parallel it is preferred.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the multiplier according to the present invention will be described as follows.

2 is a block diagram of a multiplier according to the present invention, in which a bit generator 20, first and second registers 22 and 24, and N registers 60, 62, 64, 66, ... The first shift register 26, the multiplexer 40, the logical product 28 consisting of N AND gates 70, 72, 74, 76, ..., adder 30, [N / 2 = K] (where [K] represents a positive integer rounded to K) Third register 32 consisting of registers 80, 82, 84, ..., a predetermined number of registers And a second shift register 34 composed of (90, 92, 94, 96, 98, ...), a fourth register 36, and a timing controller 38.

The multiplier shown in FIG. 2 and the multiplication method performed in the multiplier can be applied to an audio codec used in a multimedia sound card or a digital / analog converter (hereinafter referred to as DAC) for audio. A DAC is provided inside the audio codec for audio volume control. That is, although not specifically illustrated, an attenuator is provided in the DAC for audio or the DAC inside the CODEC to control the audio volume. Here, the attenuator may be implemented as a register and the multiplier and may be controlled to increase or decrease the audio volume by multiplying the input data by a control value.

Referring to FIG. 2, the first register 22 inputs in parallel the first data X of M bits, where M is a positive integer of at least one, until the multiplier finishes the multiplication operation. . The second register 24 inputs the second data Y of N bits (where N is a positive integer of at least one or more bits) in parallel and stores the multiplication operation similarly to the first register 22 until the multiplication operation is completed. do. Here, the second register 24 continuously latches the data until the register control clock (not shown) output from the timing controller 38 changes, that is, until a new second data is inputted, and latched parallel data. Are output as one input of the AND gate, respectively.

Meanwhile, the bit generator 20 generates extension bits for extending the most significant bit of the first data. If the first data has two's complement form and the most significant bit value is '1', '1' is generated as an extension bit, but otherwise, '0' is generated as extension bits. That is, the value of '0' or '1' is extended to increase the number of bits in consideration of the carry data generated by the result calculated in the lower bits.

The multiplexer 40 inputs the extension bit and the first data output from the first register 22 in parallel and sequentially inputs the input bits from the least significant bit to the most significant bit in response to the first control clock CK1. Output The first shift register 26 is reset in response to the reset signal RESET. The first shift register 26 shifts the bits output in series from the multiplexer 40 to the right by right, thereby logically multiplying the shifted N bits of shifting data in parallel. Output to the corresponding AND gate of (28). Each time the first shift register 26 shifts data by one bit, the first shift register 26 outputs the data to the logical product 28 in parallel. Here, the number of registers of the first shift register 26 changes depending on the size of the input second data.

Meanwhile, each of the N AND gates 70, 72, 74, 76,..., The shifting data output in parallel from the first shift register 26 and the second data latched in the second register 24. Y) is ANDed and the result of AND is output to the adder (30). Here, each AND gate is controlled by the corresponding bit of the second data output from the second register 24. That is, only the value of the number of bit digits whose second data is '1' is output to the adder 30 of the next stage. The adder 30 inputs and adds the outputs of the N AND gates and bits except the least significant bit in the third register 32 as carry data, and latches the added result in the third register 32. Here, the remaining digits except the least significant 1 bit of the added result bits are carry data generated in the previous operation and are fed back to add to the next operation.

The size of the third register 32 changes as the number of bits input to the adder 30 increases. That is, the number of registers of the third register 32 is [K / 2] when the number of bits input to the adder 30 is K. If the number of inputs of the adder is six, the number of registers of the third register 32 is three.

The second shift register 34 is reset in response to the reset signal RESET, and serializes the least significant bit of the added result stored in the register 80 of the third register 32 in response to a control clock for adjusting an internal operation. Shifting to transfer the data in the digit direction of the MSB bit in the LSB, and outputs the final operation result to the fourth register 36 in parallel when the internal operation is finally performed.

The fourth register 36 latches the parallel bits output from the second shift register 34 as a result of the final multiplication of the first data and the second data and through the output terminal OUT in response to the second control clock CK2. Output

Meanwhile, the timing controller 38 controls the multiplexer 40 to sequentially output the bits inputted in series so that the multiplication result latched to the first control clock CK1 and the fourth register 36 is output. A second control clock CK2 is generated, and a reset signal is generated to reset the first and second shift registers 26 and 34 before the next multiplication operation. Here, the master clock to be used may generally use a clock used in a digital audio device.

In order to help understand the operation of the multiplier according to the present invention illustrated in FIG. 2 described above, the multiplication operation of the multiplier shown in FIG. 2 when the first data is '010111' and the second data is '1010' is described. Take a look at the following: If the input data is 2's complement data, a conversion unit for converting to 2's complement data is added to the multiplier shown in FIG.

First, the first and second registers 22 and 24 latch '010111' and '1010', respectively, and the multiplexer 40 inputs data consisting of a bit string of '00 0001 0111 'in parallel. Here, four bits have been extended by the bit generator 20. The first shift register 26 inputs and shifts the serial output of the multiplexer 40, and then outputs the bits as shown in Table 1 to the corresponding AND gate.

Output of the first shift register Corresponding AND gate of logical product 28 00 1011 1000 76 00 0101 1100 74 00 0010 1110 72 00 0001 0111 70

As shown in Table 1, for example, bits are input to the AND gate 76 of the logical product 28 in the order of '0001 1101 00'.

Each AND gate of the AND product 28 logically multiplies the bits output from the first shift register 26 and the second data '1010' latched in the second register 24 in the order shown in Table 1 below. At this time, since the second data is '1010', only the outputs of the second and fourth registers 62 and 66 of the first shift register 26 are output to the adder 30, and the first and third registers 60 and The output of 64 does not mean anything because it is not output to the adder 30. The adder 30 inputs and adds the output result of the first shift register 26, latches only the least significant bit in the second shift register 34 at the rear end, and data composed of the other most significant bits are generated during operation. The data is fed back to the adder 30 as carry data, and added to the next higher-order operation. As such, when all of the first data stored in the first register 22 is calculated, the value of '00 0111 0011 'is finally latched in the fourth register 36.

As described above, the multiplier according to the present invention is inexpensive, and the size is reduced, which has a considerably advantageous effect when implementing an integrated circuit.

Claims (2)

In a multiplier that multiplies the first data of M bits, where M is at least one positive integer, and the second data of N bits, where N is at least one positive integer, A first register to input and latch the first data in parallel; Bit generation means for generating extension bits for extending the most significant bit of the first data; Parallel to serial conversion means for inputting the extended data and the first data output from the first register in parallel and sequentially outputting the input bits in series in response to an output control signal; A second register configured to input and latch the second data in parallel; First shifting means reset in response to a reset signal and outputting N-bit shifting data in parallel shifting the serial output of the parallel-to-serial conversion means; N AND products for ANDing the shifting data and the second data latched in the second register; Adding means for adding the output of the N logical multiplication means and carry data, and outputting the added result; A third register for latching bits except the least significant bit of the added result as the carry data; A fourth register for latching the least significant bit of the added result; Second shifting means reset in response to the reset signal and shifting an output of the fourth register; A fifth register configured to input the outputs of the second shifting means in parallel and latch the result of the multiplication of the first data and the second data; And And control means for generating said output control signal and generating said reset signal before a next multiplication operation. It is provided inside the digital / analog converter of the audio codec for audio volume control, wherein the first data of M bits, where M is at least one positive integer, and the N bits, where N is at least one quantity. In the multiplication method performed in the multiplier for multiplying the second data of the bit) Mixing extension bits for expanding the first data and the most significant bit of the first data; Converting the mixed parallel data into serial data; Shifting the serial data to convert it into N-bit parallel data; Logically multiplying the N bits of parallel data with the second data; Adding carry data and the result of the AND product of the previously added result; Shifting a least significant bit of the added result bits and latching bits except the least significant bit as the carry data; And And latching the shifted least significant bits in parallel as a result of the multiplication of the first data and the second data.

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