JP2591113B2 - Hamming encoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a Hamming encoder having m check bits of a generator polynomial in an exclusive-OR format, and aims to provide a Hamming encoder having a small circuit scale. The serial input information bits are sequentially input to the selector, and are taken in and held in the shift register by k clocks, and the outputs of the k information bits of the shift register are output to the k input bits of the mask signal, respectively. The AND circuit inputs the outputs of the k AND circuits to a tournament-type exclusive-OR circuit group, and sequentially selects m check bits generated by the exclusive-OR circuits in the selector. And the selector outputs the k information bits, and then selects and outputs the m check bits.

[Industrial applications]

The present invention relates to an improvement of a Hamming encoder having m check bits of a generator polynomial in an exclusive-OR form.

A Hamming code is a code capable of detecting and correcting a 1-bit error, and adding m check bits to k information bits and giving a certain relation to the whole to form a code of n = k + m bits. The receiving side detects whether or not the relationship is satisfied, and if there is an error, detects the number of the bit, and it is desired that the circuit scale can be reduced.

[Conventional technology]

 Hereinafter, a conventional example will be described with reference to the drawings.

FIG. 6 is a block diagram of a conventional Hamming encoder, FIG. 7 is a time chart of FIG. 6, and FIG. 8 shows detection of an error occurrence bit when an example generating polynomial has an exclusive OR form. FIG.

FIG. 6 shows a 7-bit Hamming code composed of four information bits A, B, C, and D and three check bits E, F, and G. The generating polynomial of check bits E, F, and G is It is of the exclusive OR type.

E = D ○ C ○ B F = D ○ C ○ A G = D ○ B ○ A 示 す indicates exclusive OR.

A, B, C, D as shown in FIG.
When these four information bits are input, they are input to the shift register 10 as shown in FIG. 7B and are sequentially input to the selector 12 from the output QA and output.

When the information bits of A, B, C, and D are input to the shift register 10, the information bits D, C, and B are converted to an exclusive OR circuit ( EX-OR below
), And the information bits D, C, and A are generated by a generator polynomial D ○ C ○ A for the check bit F.
In this case, the information bits D, B, and A are input to an EX-OR set 31 composed of EX-ORs 24 and 25. The test signal is input to an EX-OR set 32 composed of ORs 26 and 27, check bits E, F, and G are obtained from the outputs of the EX-OR sets 30, 31, and 32. (C), the shift register
28 is input in parallel, and E, F, and G are output in series in this order from the output.

At this time, the select signal from the timing signal generating circuit 20-2 goes high as shown in FIG.
As shown in FIG. 7 (E), the selector 12 outputs information bits A, B, C, D and check bits E, F, G in that order and performs Hamming encoding.

For the information bits A, B, C, D, the generator polynomial of the check bits E, F, G is, as shown in FIG. 8 (A), E = D ○ C ○ B, F = D
ＣC ○ A, G = D ○ B ○ A, the transmission Hamming code is A, B, C, D, E, F, G as shown in FIG. 8 (B), and the received Hamming code is (C). As shown in A, B ', C', D ', E', F ',
G ', and when a 1-bit error occurs as shown in the left column of (D), the state of the check bit when re-encoding the error-occurring bit is, for example, as shown in the right column of (D), If not, E ', F', G 'are equal to E ", F", G ", respectively, but if A ≠ A', E '≠ E", G' ≠ G "
When B ≠ B ′, F′ＦF ″ and G ′ ≠ G ″. It is as shown in the figure below.

That is, when a 1-bit error occurs, the received check bits E ', F', G 'and the re-encoded check bits E ", F",
There is a case where G "is equal to or different from G", and the position of the error bit can be detected and corrected based on the content.

[Problems to be solved by the invention]

However, since a generator polynomial is simultaneously generated and output for each check bit, the number of EX-OR circuits is large, and a shift register for simultaneously inputting each check bit generated in parallel and outputting it in series is provided. There is a problem that the circuit scale becomes large as necessary.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a Hamming encoder having a check bit of a generator polynomial in an exclusive OR format having a small circuit scale.

[Means for solving the problem]

1A and 1B are principle diagrams of the present invention, wherein FIG. 1A is a block diagram showing the configuration, and FIG. 1B is a time chart.

As shown in FIG. 1A, k information bits input in series are sequentially input to a selector 12, and are taken in and held by a shift register 10 with k clocks. The output of each information bit is input to k AND circuits 1, 2,..., K−1, k to which a mask signal is input from the timing signal generation circuit 20, respectively.
The outputs of the AND circuits 1, 2,..., K−1, k are input to the exclusive OR circuit group 11 in the tournament format.

Then, the mask signal input to the k AND circuits 1, 2,...
At the timing at which m check bits are sequentially obtained, at each timing, a signal for masking irrelevant information bits is used as a signal, and the m check bits generated by the exclusive OR circuit group 11 are sequentially output to output the m check bits. Input to selector 12.

Then, after outputting the k information bits, the selector 12 selects and outputs the m check bits.

(Operation)

In the present invention, serially input k information bits shown in (a) of FIG.

On the other hand, the k information bits are represented by k shown in (b) of (B).
(C) of (B) in the shift register 10
As shown in the figure, it is taken and held.

The k information bits held in the shift register 10 are respectively input to k AND circuits 1, 2,..., K−1, k to which a mask signal is input from the timing signal generation circuit 20.

Assuming that the mask signal input to the AND circuit is L level, the information bit input to the AND circuit is not output and the output is at L level. In the EX-OR circuit, one input level is Focusing on the point that the other input outputs through when the level is at the L level, the k AND circuits 1, 2,.
The mask signal shown in (d) of (B) input to k−1, k is obtained at the timing of sequentially obtaining m check bits by the timing signal generation circuit 20. Is a signal to be masked.

In this case, m check bits of the generator polynomial in the exclusive-OR format are sequentially output from the output of the EX-OR circuit group 11 in the tournament format and input to the selector 12.

The selector 12 receives a selection signal as shown in (e) of (B), and outputs a selection signal as shown in (f) of (B) rather than the output.
Next to the k information bits, m check bits are selectively output and transmitted as a Hamming code.

In this way, using a logical product circuit, a mask signal to be input to the logical product circuit is generated at the timing when m check bits are sequentially obtained.
At each timing, irrelevant information bits are masked, so that m check bits are not generated at the same time.
Since the check bits are sequentially generated, the number of EX-OR circuits for obtaining the exclusive-OR generating polynomial can be reduced, and the check bits of the m generating polynomials can be simultaneously and in parallel. Since a shift register for inputting and serially outputting is unnecessary, the circuit scale can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a Hamming encoder according to an embodiment of the present invention, FIG. 3 is a time chart in the case of FIG. 2, and FIG. 4 is an example of a Hamming encoder illustrating one stage of the present invention. FIG. 5 is a time chart of FIG.

2 and 4 show four information bits as in the conventional example.
This is a case of a 7-bit Hamming code composed of A, B, C, D and three check bits E, F, G of a generator polynomial in an exclusive OR form.

First, a method for eliminating a shift register for converting a parallel input into a serial output will be described with reference to FIGS.

In FIG. 4, when the information bits of A, B, C, and D shown in FIG. 5A are input, they are input to the selector 12 and output.

On the other hand, this information bit is used for the timing signal generation circuit 20-.
The four control clocks shown in FIG. 5 (B) are input to and held in the shift register 10 as shown in FIG. 5 (C).

Using the output of the shift register 10 to generate the check bits E, F, and G of the generator polynomial in the exclusive-OR format is the sixth
Check bits generated in the same manner as the conventional example in FIG.
E, F, and G are input to the selector 21.

As shown in FIG. 5 (SEL1), (SEL2) and (SEL3), the selector 21 outputs a signal for sequentially selecting and outputting the check bits E, F, and G from the timing signal generation circuit 20-1. Therefore, the selector 21 sequentially outputs check bits E, F, and G.

Since the selection signal output from the timing signal generating circuit 20-1 as shown in FIG. 5D is input to the selector 12, the selector 12 outputs the information bits A and A as shown in FIG. Check bits E, F, and G are output next to B, C, and D, and become a Hamming code.

That is, as shown in FIG. 5 (SEL1) (SEL2) (SEL3),
If the check bits E, F, and G are sequentially selected and the check bits E, F, and G are sequentially obtained in accordance with the timing of the signal to be output, the shift register of the parallel input serial output can be eliminated. In the embodiment of the present invention shown in FIGS. 2 and 3,
In addition to using the signal of the timing of sequentially outputting the check bits E, F, and G, the check bits E, F, and G are not generated at the same time, but are sequentially generated according to this timing.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

In FIG. 2, when the information bits of A, B, C, and D shown in FIG. 3A are input, they are input to the selector 12 and sequentially output.

As shown in FIG. 3C, four control clocks from the timing signal generating circuit 20 shown in FIG.
The data is input to the shift register 10 and held.

The output of the shift register 10 is input to the AND circuits 1, 2, and 3 with information bits A, B, and C, and the information bit D is a check bit E,
Since it is not necessary to use a mask in all cases of F and G, the EX-OR circuit 41 of the EX-OR circuit group 11 in the tournament format as it is
To enter.

The AND circuits 1, 2, and 3 use the signal from the timing signal generation circuit 20 as shown in FIGS. 3 (DEC1), (DEC2), and (DEC3) to generate the L level at the timing of generating the check bits E, F, and G. The mask signals DEC1, DEC2, and DEC3 are input from the decoder 13.

Now, the case where the mask signal DEC1 is at the L level will be described. The information bit A is masked and is not output from the AND circuit 1, and the output of the AND circuit 1 is at the L level.

Then, the information bit B output from the AND circuit 2 becomes
The EX-OR circuit 40 takes a through signal and inputs it to the EX-OR circuit 42.

On the other hand, the information bit C output from the AND circuit 3 is EX
-Input to the OR circuit 41.

This state is the same as the state of the EX-OR set 30 in FIG. 6, and the check bit E of the generator polynomial DＣC ○ B is output from the output and input to the selector 12.

At this time, since a signal for selecting a check bit as shown in FIG. 3D is input to the selector 12, the information bit E is output from the selector 12.

When the mask signals DEC2 and DEC3 become L level as shown in FIGS. 3 (DEC2) and (DEC3), the generator polynomial D.sub.C.sub.C.sup.
The check bits F and G of A, D ○ BＡA are generated, and the selector 1
Output from 2.

That is, the output of the selector 12 is as shown in FIG.
A, B, C, D, E, F, and G hamming codes.

The inside of the decoder 13 is a normal one using NAND circuits 14 to 16 and knot circuits 17 and 18.

Thus, comparing the circuit scales in the case of FIGS. 2 and 6, in the case of FIG. 6, 4 × 6 = 24 BC with six EX-OR circuits.
(Basic cell), and the shift register 28 is 24BC, for a total of 48BC. In the case of FIG. 2, the decoder 13 is 5BC, 3 AND circuits, 2 × 3 = 6BC, and 3 EX-OR circuits, 4 ×
3 = 12BC for a total of 23BC, reducing the circuit size by 25BC.

This reduction in circuit size becomes more pronounced as the number of check bits is larger and the Hamming code has a larger number of bits.

〔The invention's effect〕

As described above in detail, according to the present invention, there is an effect that a Hamming encoder having a small circuit scale and having a check bit of a generating polynomial in an exclusive OR form can be obtained.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram of a Hamming encoder according to an embodiment of the present invention, FIG. 3 is a time chart in the case of FIG. 2, and FIG. FIG. 5 is a time chart of FIG. 4, FIG. 6 is a block diagram of a conventional Hamming encoder, and FIG. 7 is a time chart of FIG. FIG. 8 is a diagram showing the detection of an error occurrence bit when the generator polynomial in one example is in the exclusive-OR format. In the figure, 1,2,3, k−1, k are AND circuits, 10,28 are shift registers, 11 is a tournament-type exclusive OR circuit group, 12,21 is a selector, 13 is a decoder, 14 ~ 16 is a NAND circuit, 17, 18 is a knot circuit, 20, 20, -1, 20-2 are timing signal generation circuits, 22 to 27, 40 to 42 are exclusive OR circuits, 30, 31, and 32 are exclusive logic. 3 shows a set of sum circuits.

Claims (1)

(57) [Claims] (1) k (k = nm, n is the number of Hamming code bits,
m = the number of check bits) serial input information bits are sequentially input to the selector (12), and the shift register (10)
And the output of each of the k information bits of the shift register (10) is k ANDed with the mask signal input from the timing signal generation circuit (20). Input to the circuit (1,2, ... k-1, k)
The outputs of the k AND circuits (1, 2,..., K−1, k) are input to a tournament-type exclusive OR circuit group (11),
The mask signals input to the k AND circuits (1, 2,..., K−1, k) are changed by the timing signal generation circuit (20) at the timing of sequentially obtaining m check bits. At each timing, an irrelevant information bit is masked, and m check bits generated by the exclusive OR circuit group (11) are sequentially input to the selector (12). )), After outputting the k information bits,
A Hamming encoder characterized in that a plurality of check bits are selected and output.