JPH04265011A - White noise generator - Google Patents

Abstract

PURPOSE:To obtain a generator suitable for IC conversion by comparing values before and after the output noise of a noise generator, inverting a flip-flop, when they coincide with each other, and setting it to a state as it is in the case of noncoincidence. CONSTITUTION:The noise generator for generating a random noise extending over a wide band is constituted of a first - a fifth D-FFs (D type flip-flop circuits) 1 to 5 which are cascaded, inverters 6-10 connected between each stage, and EOR gates 11-13. A detecting circuit 15 compares the values before and after-output noise signal of the noise generator, and detects whether they coincide or do not coincide with each other. Also, this noise generator is provided with a flip-flop circuit 20 in which a state is varied in accordance with a detection output for showing the coincidence of the circuit 15, and the state is not varied in accordance with a detection output for showing the noncoincidence. According to this constitution, a white noise which is suitable for IC conversion, and also, in which a frequency spectrum distribution is dense can be obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a white noise generator that generates random white noise, and particularly to a white noise generator suitable for use in an IC.

0002

2. Description of the Related Art A white noise generator that generates white noise using a cyclic shift register is known. Figure 2 shows a white noise generator configured with 5 bits, and the first to fifth D bits are continuously connected.
-FF (D-type flip-flop circuit) (1) to (5)
and inverters (6) to (10) connected between each stage.
, EOR gates (11) to (13), and a low-pass filter (100). In FIG. 2, when a clock signal is applied from the clock terminal (14),
The clock signal is applied to the first to fifth D-FFs (1) to (5).
), and the input signal is transferred to the output terminal in response to the falling edge of the clock terminal (Cl). 5th D-FF
The Q5 output of (5) is applied to the D terminal of the first D-FF (1), so the output circulates. Also, the 5th D-FF
The Q5 output of (5) is the EOR gate (11) to (13).
), which causes the value of each Q output to be generated randomly. The values of each Q output have different generation timings, but have the same repeating pattern, and noise can be obtained by selecting one of them.

In the example of FIG. 2, the Q1 output of the first D-FF (1) is taken out, passed through a low-pass filter (100), and taken out to the output terminal (101). The low-pass filter (100) is for making the spectrum distribution in the output white noise component constant. That is, the above Q
As shown in FIG. 3, the spectrum distribution of one output becomes unfavorable because the higher the frequency band, the sparser the distribution becomes. Therefore, it is necessary to extract only the components in the low frequency band where the distribution is dense. Therefore, a low-pass filter (100) with characteristics as shown by the dotted line in FIG. 3 is required, and its output becomes high-quality white noise with a dense distribution of frequency components.

Although FIG. 2 shows a noise generator composed of 5 bits, in order to obtain noise (random numbers) with a frequency over a high band, the frequency of the clock signal must be set to 30K.
It is sufficient to set the frequency to about Hz and the number of D-FF stages to about 15. In this way, a value sufficient for use as white noise can be obtained.

[0005]

However, when implementing the circuit shown in FIG. 2 into an IC, there is a problem in that the value of the capacitor of the low-pass filter (100) is relatively large, so it cannot be incorporated into the IC. The Q output of the circuit of FIG. 2 is a digital value. If it is a digital value, S-Z
One possibility is to use a digital filter that uses exchange. A digital filter can be built into an IC. However, such a digital filter requires a huge number of elements, which is problematic.

[0006]

[Means for Solving the Problems] The present invention has been made in view of the above points, and provides a noise generator that generates random noise over a wide band, and values before and after the output noise signal of the noise generator. a detection circuit that compares and detects whether there is a match or a mismatch, and a state that changes depending on a detection output from the detection circuit that indicates a match, and a state that changes depending on a detection output that shows a mismatch from the detection circuit. and a flip-flop circuit that does not change, and is characterized in that the output of the flip-flop circuit is output as white noise.

[0007]

According to the present invention, the output noise values of the noise generator are compared, and if they match, the flip-flop is inverted, and if they do not match, the state is left as is. Therefore, the output component of the flip-flop no longer contains high frequency components, and white noise with a dense spectrum distribution is obtained.

[0008]

[Embodiment] Figure 1 is a circuit diagram showing an embodiment of the present invention.
15) consists of the 6th and 7th D-FFs (16) and (17) that shift register the Q1 output of the 1st D-FF (1), and the 1st and 2nd AND gates (18) and (19). A detection circuit that compares the values before and after the signal and detects a match/mismatch, and an RS (20) that is inverted according to the detection output of the detection circuit (15) and generates white noise at the output terminal (21). -FF.

In FIG. 1, circuit elements that are the same as those in FIG. 2 are designated by the same reference numerals and their explanations will be omitted. Now, a clock signal as shown in FIG. 4(a) is applied from the clock terminal (14) to the first to fifth D-FFs (1) to (5) and the sixth and seventh D-FFs (16) and (17). , it is assumed that the output shown in FIG. 4(b) is generated as the Q1 output. Figure 4 (
The signal of (b) is the 6th D-FF (1) in the detection circuit (15).
6), as shown in Figure 4(c), and further 7D-F
It is applied to F(17) and the result is as shown in FIG. 4(d). and,
The Q6 output and the Q7 output are applied to the first AND gate (18), and the output is as shown in FIG. 4(E). Also, the *Q6 output and *Q7 output are applied to the second AND gate (19), and the output is as shown in FIG. 4(f). The signal in FIG. 4(e) is applied to the RS-FF (20) as a set signal,
The signal in Fig. 4 (F) is used as a reset signal for RS-FF (2
0). The RS-FF (20) is initially in a reset state and in a rising operation. Therefore, the Q output of the RS-FF (20) is as shown in FIG. 4 (G). Here, when comparing FIG. 4(B) and FIG. 4(G), pulses A and B in FIG. 4(B) disappear in FIG. 4(G). Pulses A and B in FIG. 4(b) have shorter periods and higher frequencies than pulses C and D. Therefore, it is clear that only high frequency components disappear.

[0010] Therefore, the detection circuit (15) and the RS-FF
Due to (20), only white noise with low frequency components is passed, and white noise with a dense spectrum distribution can be obtained at the output terminal (21). still,
In the embodiment shown in FIG. 1, the values before and after are compared based on the difference in time of two clocks, but the time may be increased by three or four clocks. By doing so, noise of low frequency components will be passed. Further, in the embodiment shown in FIG. 1, the Q1 output is used, but any of the Q2 to Q5 outputs may be used.

[0011]

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a white noise generator that does not require a capacitor, is suitable for IC implementation, and can generate white noise with a dense frequency spectrum distribution. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a white noise generator of the present invention.

FIG. 2 is a block diagram of a conventional white noise generator.

FIG. 3 is a characteristic diagram showing frequency components of an output signal of the circuit in FIG. 2;

FIG. 4 is a waveform diagram for explaining FIG. 1;

[Explanation of symbols]

(15) Detection circuit (20) RS-FF

Claims (2)

[Claims] 1. A noise generator that generates random noise over a wide band, and a detection circuit that compares the values before and after the output noise signal of the noise generator to detect whether they match or do not match. , a flip-flop circuit whose state changes in response to a detection output indicating a match of the detection circuit, and whose state does not change in response to a detection output of the detection circuit indicating a mismatch; A white noise generator characterized by outputting as follows. 2. The detection circuit comprises a plurality of cascade-connected D-type flip-flops and an AND gate to which Q outputs before and after the plurality of D-type flip-flops are applied. The white noise generator described in 1.