JPH0514153A - Two-phase clock signal generating circuit - Google Patents

Abstract

PURPOSE:To generate complementary two-phase clock signals changing simultaneously in which there is no time difference between an output of a noninverting clock signal and an output of an inverting clock signal. CONSTITUTION:An in-phase signal resulting from a signal given to a lock signal input terminal 1 passing through 2-stages of inverse logic elements 4, 5 and an in-phase signal resulting from the signal given to the clock signal input terminal 1 passing through 4-stages of inverse logic elements 4, 6, 7, 8 are synthesized and the in-phase clock signal is generated at an output terminal 2. Simultaneously, an antiphase signal passing through 3-stages of inverse logic elements 4, 6, 7 is outputted to the output terminal 3 as an antiphase clock signal. Thus, the complementary two-phase clock signals changing simultaneously in which there is no time difference between an output of an in-phase clock signal and an output of an antiphase clock signal are generated by receiving a single-phase clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-phase clock signal generation circuit for generating a positive-phase and negative-phase complementary clock signal from a single-phase clock signal input in a digital circuit.

[0002]

2. Description of the Related Art In recent years, with the progress of digitization of electronic devices, the accuracy of analog / digital converters (A / D converters) and digital / analog converters (D / A converters), which are the key devices, has been improved. Has come to be required. In order to improve the accuracy of the D / A converter, it is necessary to improve the accuracy of the two-phase clock signal generation circuit that controls the switching timing of the current switch that is a component thereof.

A conventional two-phase clock signal generation circuit will be described below with reference to FIGS. 2 and 4. FIG. 2 is a diagram showing an example of the configuration of a conventional two-phase clock signal generation circuit, and FIG. 4 is a diagram showing waveforms at respective nodes of the conventional two-phase clock signal generation circuit.

In FIG. 2, 1 is a clock signal input terminal, 2 and 3 are clock signal output terminals, and 4 to 7 are inverting logic elements. In FIG. 4, 9 is the waveform of the output signal obtained at the clock signal output terminal 3 of FIG. 2, and 10 is the waveform of the output signal obtained at the clock signal output terminal 2 of FIG.

In the two-phase clock signal generation circuit shown in FIG.
First, the signal at the clock signal input terminal 1 goes high
Bell (V_H) To low level (V_L) Changes to reverse
The output of the logic element 4 is the propagation delay (τ_d) Time delay
At low level (V_L) To high level (V_H)
It The signal output to the clock signal output terminal 2
Is the time due to the propagation delay of a total of two stages of inverting logic elements 4 and 5.
Delay (2τ_d) At high level (V_H) To low level
(V_L). On the other hand, the clock signal output terminal 3
The output signal is a total of three stages of inverting logic elements 4, 6 and 7.
Delay due to the propagation delay of (3τ_d) At low level
(V_L) To high level (V_H). That is,
Clock signal is output for the lock signal input terminal 1 signal
2τ for force terminal 2 _dIn-phase signal 10 is output due to the time difference of
And 3τ at the clock signal output terminal 3._dOpposite phase due to time difference
The signal 9 is output.

By the above operation, the complementary two-phase clock signal is generated from the single-phase clock signal input signal.

[0007]

However, in the above-mentioned conventional configuration, the number of inverting logic elements between the clock signal input terminal 1 and the clock signal output terminal 2 (positive phase) and the clock signal output terminal 3 are required. Since there is a difference in the number of inverting logic elements between (reverse phase), there is a difference in the propagation delay of each signal. In other words, there is a problem in that the positive-phase clock signal and the negative-phase clock signal do not change at the same time, and the positive-phase clock signal output and the negative-phase clock signal output have a propagation delay difference (τ _d ) corresponding to one stage of the inverting logic element. It was

The present invention solves the above-mentioned conventional problem, and there is no time difference between the positive-phase clock signal output and the negative-phase clock signal output, and it is possible to generate a complementary two-phase clock signal that changes simultaneously. An object is to provide a clock signal generation circuit.

[0009]

To achieve the above object, in a two-phase clock signal generating circuit of the present invention, a signal applied to a clock signal input terminal is a positive-phase signal which passes through two inverting logic elements. A positive phase signal that has passed through four stages of inverting logic elements is synthesized to generate a positive phase clock signal, and at the same time, a negative phase signal that has passed through three stages of inverting logic elements is made into a negative phase clock signal. ..

[0010]

With this configuration, it is possible to generate a complementary two-phase clock signal in which the single-phase clock signal is input and the positive-phase clock signal output and the negative-phase clock signal output change simultaneously with no time difference.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a configuration of a two-phase clock signal generation circuit in this embodiment, and FIG. 3 is a diagram showing waveforms at respective nodes in this embodiment.

In this embodiment, an inversion logic element 8 is inserted and connected between the output terminals of the inversion logic elements 5 and 7 of the two-phase clock signal generating circuit having the configuration shown in FIG.

In FIG. 3, 11 is the waveform of the output signal of the inverting logic element 5 when the output of the inverting logic element 8 and the output of the inverting logic element 5 are not coupled, and 12 is the output signal of the inverting logic element 8 at that time. A waveform 13 is a waveform of the output signal obtained at the clock signal output terminal 2 which is a combination of the output signals 11 and 12.

In the present embodiment, first, when the input signal applied to the clock signal input terminal 1 changes from the high level (V _H ) to the low level (V _L ), the output of the inverting logic element 4 corresponds to its propagation delay ( It changes from the low level ( _VL ) to the high level ( _VH ) with a time delay of τ _d ). The output signal obtained at the clock signal output terminal 3 is the inverting logic element 4,
Time delay (3τ _d ) due to propagation delay of a total of 3 and 6 stages
Changes from low level ( _VL ) to high level ( _VH ). On the other hand, in FIG. 1, assuming that the output of the inversion logic element 5 and the output of the inversion logic element 8 are not coupled, the output of the inversion logic element 5 is the time due to the propagation delay of a total of two stages of the inversion logic elements 4 and 5. With a delay (2 τ _d ), the output changes from the high level (V _H ) to the low level (V _L ) as shown by the signal waveform 11 in FIG.
With a time delay (4τ _d ) due to a total of four stages of propagation delay,
As shown by the signal waveform 12 in FIG. 3, the high level (V _H ) changes to the low level (V _L ).

In this embodiment, the outputs of the inverting logic element 5 and the inverting logic element 8 are combined at the clock signal output terminal 2, and the signal at the clock signal output terminal 2 is, as shown in FIG. The output signal of 5 and the output signal of the inverting logic element 8 become a composite (average voltage) signal 13, and equivalently, from a high level (V _H ) to a low level with a time delay (3τ _d ) due to the propagation delay of three stages of inverting logic elements. It changes to the level ( _VL ).
That is, the in-phase signal is output to the clock signal output terminal 2 with a time difference of 3τ _d with respect to the signal of the clock signal input terminal 1, and at the same time, the anti-phase signal is output to the clock signal output terminal 3 with an equal time difference of 3τ _d. Is output.

As described above, according to this embodiment, a signal applied to the clock signal input terminal is combined with a positive phase signal having two stages of inverting logic elements and a positive phase signal having four stages of inverting logic elements. Generate a positive-phase clock signal, and at the same time generate a negative-phase clock signal that is a negative-phase signal that has passed through three stages of inverting logic elements, the single-phase clock signal is input and the positive-phase clock signal output and the negative-phase clock signal are input. It is possible to generate a complementary two-phase clock signal in which signal outputs have no time difference and change simultaneously.

[0017]

According to the present invention, the positive phase clock signal is obtained by synthesizing the positive phase signal in which the signal applied to the clock signal input terminal passes through the inverted logic element in two stages and the positive phase signal in which the signal passed through the inverted logic element in four stages. At the same time as generating the, the configuration in which the anti-phase signal that has passed through three stages of the inverting logic element is the anti-phase clock signal,
It is possible to realize an excellent two-phase clock signal generation circuit that can input a single-phase clock signal and generate a complementary two-phase clock signal in which the positive-phase clock signal output and the negative-phase clock signal output change simultaneously with no time difference. is there.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a two-phase clock signal generation circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional two-phase clock signal generation circuit.

FIG. 3 is a diagram showing waveforms at each node in the embodiment of the present invention shown in FIG.

FIG. 4 is a diagram showing a waveform of each node in a conventional two-phase clock signal generation circuit.

[Explanation of symbols]

 1 clock signal input terminal 2 and 3 clock signal output terminal 4 to 8 inverted logic element

Claims (1)

Claim: What is claimed is: 1. A first inverting logic element having an input terminal connected to a clock signal input terminal, an input terminal connected to an output terminal of the first inverting logic element, and an output terminal A second inverting logic element connected to the first clock signal output terminal,
A third inverting logic element whose input terminal is connected to the output terminal of the first inverting logic element, and whose input terminal is connected to the output terminal of the third inverting logic element and whose output terminal is the second clock signal. A fourth inverting logic element connected to the output terminal,
A two-phase clock signal generation circuit having an input terminal connected to an output terminal of the fourth inverting logic element and an output connected to an output terminal of the second inverting logic element.