JPS5829234A - Information transmitter - Google Patents

Information transmitter

Info

Publication number
JPS5829234A
JPS5829234A JP12856881A JP12856881A JPS5829234A JP S5829234 A JPS5829234 A JP S5829234A JP 12856881 A JP12856881 A JP 12856881A JP 12856881 A JP12856881 A JP 12856881A JP S5829234 A JPS5829234 A JP S5829234A
Authority
JP
Japan
Prior art keywords
data
circuit
outputs
counter
transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12856881A
Other languages
Japanese (ja)
Inventor
Sumiyoshi Yoshino
吉野 純由
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP12856881A priority Critical patent/JPS5829234A/en
Publication of JPS5829234A publication Critical patent/JPS5829234A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/45Transmitting circuits; Receiving circuits using electronic distributors

Abstract

PURPOSE:To make work easy by making the number of wires between a transmitting and a receiving circuits less than the number of data to be transmitted. CONSTITUTION:When a transmission command signal is supplied, a pulse generating circuit P generates a clock pulse. The clock pulse is supplied to the (n)- scale counter CT on a transmission side and also sent the a receiving circuit II'. The counter CT counts the clock pulses to generate count outputs B, C and D. Then, AND gates GT1-GTn on the transmission side are opened in response to count outputs 1-(n) of the counter CT to allow (n) pieces of data to pass through them, and when those (n) data are arranged in time series at a data output terminal TT2, split (n)-multiple data E are obtained. In the receiving circuit II', on the other hand, the clock pulses sent from a transmtting circuit I' are counted by an (n)-scale counter CR to generate count outputs F, G, and H. Then, (n) gates GR1-GRn are opened in response to count outputs 1-(n) of the counter CR to obtain (n)-multiple data.

Description

【発明の詳細な説明】 この発明線情報伝送装置に@するものである。[Detailed description of the invention] This is to @ the invention line information transmission device.

従来の情報伝送装置は、第1図に示すように、送信回路
1から受信回路■ヘロ個のデータを伝送するのに、i本
のデータ信号線L工〜L、と共通線L0とを合わせてn
+1本の配線が必要であり、施工が容易でなかつ九。
As shown in Fig. 1, a conventional information transmission device uses i data signal lines L to L and a common line L0 to transmit data from a transmitting circuit 1 to a receiving circuit. te n
+1 wiring is required, making installation difficult.

したがって、この発明の目的は、伝送するデータの個数
に対して送信回路および受信回路間の配線本数を少くし
て施工を容易にすることができる情報伝送装置を提供す
ることである。
Therefore, an object of the present invention is to provide an information transmission device that can be easily installed by reducing the number of wires between a transmitting circuit and a receiving circuit relative to the number of data to be transmitted.

この・発明の一実施例を第2図会よび第3図に示す、す
なわち、この情報伝送装置は、第2図に示すように、送
信指令信号にもとづいてクロックバルスを発生するパル
ス発生回路Pと、このパルス!使[路Pのクロックパル
スをカウントする送信側n進カウンタ(口は2以上の整
数)CTと、この送信側n進カウンタCTの1からnま
でのカランを出力にそれぞれ同期応答して開くことによ
り第1番目から第n番目までのn個のデータをそれでれ
通過させる第1番目から第n番目までのn個の送信側ア
ンドゲートGT工〜GTnト、1fflli3パルス発
生回路Pのりaツクパルスを出方するクロック出力端子
TT工と、前記n個′の送信側アンドゲートGT工〜G
Tnの出力を合成して時分割n重データを出力するデー
タ出力端子TT2とを有する送信回路1′と、前記りo
+yり出力端子胃、よりりq、り線LAt通してりEl
、クバルスが入力されるクロック入力端子TRユと、1
1記データ出カ端子TT2よりデー#1lLBt−通し
て時分1flln重データが入力されるデータ入力端子
TR2と、str紀りayり入カ端子TR工に与えられ
九りロ噌りバルスを前記送信側n進カウンタCTと同じ
タイミングでカウントする受信側n進カウンタCRと、
この受信側n進カウンタCRの1からntでのカウント
出力にそれぞれ同期応答して開くことによpsreデー
タ入力端子TR2に与えられた時分割n重データを通過
させて第1番目から第1■までのn個のデータを分離抽
出する第1番目から第n番目までのn個の受信側アント
ゲ−) GR工〜GRnと含有する受信回路l′とt備
えている。な訃、D0〜Dnはそれぞれダイオード、T
T3およびTR8は共通端子、Loは共通機である。
An embodiment of this invention is shown in FIGS. 2 and 3. That is, as shown in FIG. And this pulse! The transmitting side n-ary counter (integer is an integer of 2 or more) that counts the clock pulses of the path P and the counters from 1 to n of this transmitting side n-ary counter CT are opened in synchronous response to the output. Accordingly, the first to nth n transmitting side AND gates, which pass the first to nth data, are connected to the 1fflli3 pulse generation circuit P to generate a pulse. The output clock output terminal TT and the n' sending side AND gates GT ~G
a transmitting circuit 1' having a data output terminal TT2 for synthesizing the outputs of Tn and outputting time-division n-fold data;
+y output terminal stomach, twist q, twist wire LAt through El
, a clock input terminal TR to which Kubals is input, and 1
The data input terminal TR2 receives the hour/minute 1flln heavy data from the data output terminal TT2 through the data #1LBt-, and the input terminal TR is given to the input terminal TR. a receiving side n-ary counter CR that counts at the same timing as the transmitting side n-ary counter CT;
By opening in synchronous response to the count outputs from 1 to nt of the receiving-side n-ary counter CR, the time-division n-fold data applied to the psre data input terminal TR2 is passed through. n receiving circuits (first to nth) receiving circuits (1) to (n) for separating and extracting n data from GR to GRn are provided. , D0 to Dn are diodes, T
T3 and TR8 are common terminals, and Lo is a common machine.

この情報伝送装置は、パルス発生回路Pに送信指令信号
が与えられると、このパルス発生回路Pが動作を開始し
て第3図囚に示すようなりロック/< k Xを発生す
る。このクロックパルスハ送fjRIIn進カウンタC
Tへ与えられるとともに受信回路■′へ送られる。送信
側口達カウンタCTFi、クロ、クバルスをカウントし
て第3図(至)、(O9(2)に水すようなカウント出
力を発生する。送信側アンドケ−)GT工〜GTnは、
送信側n進カウンタCTの1からntでのカウント出力
にそれぞれ応答して開くことによりn個のデータをそれ
ぞれ通過させ、データ出力端子TT、に訃いてn個のデ
ータ1〜n七時系列的に避べ九第3図但)に示すような
時分割n重データを得ている。なお、第3図■のデータ
1−aは「lJ、「o」のデジタルデータである。
In this information transmission device, when a transmission command signal is given to the pulse generation circuit P, the pulse generation circuit P starts operating and generates a lock/<kX as shown in FIG. This clock pulse is sent to fjRIIn base counter C.
The signal is given to T and also sent to the receiving circuit ■'. The transmission side count counters CTFi, Kuro, and Kubalus are counted and generate count outputs as shown in Fig. 3 (to) (O9 (2)).
By opening in response to the count output from 1 to nt of the n-ary counter CT on the transmitting side, n pieces of data are respectively passed through, and n pieces of data 1 to n are sent to the data output terminal TT in a time series manner. However, time-division n-fold data as shown in Figure 3) is obtained. Note that data 1-a in FIG. 3 is digital data of "lJ" and "o".

一方、受信回路■′では、送信回路I′より送られ九り
ロ雫Jlハszスを受信側口進カウンタCR−1)Eカ
ウントして第3図便) 、 (G) 、 @ K示すよ
うな同図@λゆ−(ロ)とそれぞれ同じタイミングのカ
ウント出方をJ!生する。n個の受信側アンドグー) 
GR工>GR。
On the other hand, in the receiving circuit ■', the nine drops sent from the transmitting circuit I' are counted by the receiving side counter CR-1)E and shown as Figure 3), (G), @K. J! live. n receivers and goo)
GR engineering > GR.

ハ、受信側n進カウンタCRの1かうfltt’ノカウ
ント出力にそれヤれ応答して開くことにより時分割n重
データを通過させてn個のデータを分離抽出する。
C. It is opened in response to the 1-fltt' count output of the n-ary counter CR on the receiving side to pass time-division n-fold data and separate and extract n pieces of data.

このn個の受信側アンドグー) GRユ〜GRnの出力
であるn個のデータはそれぞれ情報処理回数図示せず)
へ供給される。
These n pieces of data on the receiving side (and-go) are the number of information processing times for each of the n pieces of data that are the outputs of GR Yu to GRn (not shown)
supplied to

このように、この実施例の情報伝送装置は、n個のデー
タをクロックパルスにもとづいて時系列的Kllべ時分
割n重信号として伝送するようにした友め、送信回路I
′と受信回路■′との間をりaツク繰LA eデータ1
lL−よび共通機L0の3本の配線で連絡するだ叶でよ
く、配線本数を従来例に比べて大幅K11ll減でき、
施工を容易に行える。
As described above, the information transmission device of this embodiment has a transmission circuit I which transmits n pieces of data as a time-sequential time-division n-fold signal based on clock pulses.
’ and the receiving circuit ■’
Only three wires (L- and common device L0) are required for communication, and the number of wires can be significantly reduced by K11ll compared to the conventional example.
Construction is easy.

以上のように、この発明の情報伝送装置は、送信指令信
号にもとづいてクロックパル′Xを発生するパルス発生
回路と、このパルス発生回路のクロックパルスをカウン
トする送信側n進カウンタ(aI/i2以上の整数)と
、この送信側n進カウンタの1からniでのカウント出
力にそれぞれ応答して開くことによりn個のデータをそ
れぞれ通過させるn個の送信側ゲートと、前記パルス発
生回路6クロツクパルスを出方するクロック出方端子と
As described above, the information transmission device of the present invention includes a pulse generation circuit that generates a clock pulse 'X based on a transmission command signal, and a transmission side n-ary counter (aI/i2) that counts the clock pulses of this pulse generation circuit. or above), n transmitting side gates that open in response to count outputs from 1 to ni of the transmitting side n-ary counter to allow n pieces of data to pass through, respectively, and the pulse generating circuit 6 clock pulses. With the clock output terminal.

前記n個の送信側ゲートの出方を合成して時分割n重デ
ータを出力するデータ出力端子とを有する送信回路と、
前記りowyり出カ鴫子よりクロック線を通してりaツ
クパルスが入力−5れるl El 91入力端子と、l
Ir紀データ出カ端子よシデータ1at−通して時分割
n重データが入力されるデータ入力端子と、前6りaツ
ク六方端子に与えられたクロックパルスをカウントする
受信111n進カウンタと。
a transmitting circuit having a data output terminal that combines the outputs of the n transmitting side gates and outputs time-division n-fold data;
A clock pulse is inputted through the clock line from the above output terminal to the El91 input terminal, and
A data input terminal to which time-division n-fold data is input through the data output terminal and data 1at-, and a reception 111n-ary counter that counts clock pulses applied to the front six-way hexagonal terminal.

この受信側n進カウンタの1からntでのカウント出力
にそれぞれ応答して開くことにより前記データ入力端子
に与えられた時分割1重データを通過させてn個のデー
タを分離抽出するn個の受信側ゲートとを有する受信回
路とを備えているので、伝送するデータの個数に対して
送信回路および受信回路間の配線本数を少くして施工を
容易にすることができるという効果がある。
n pieces of data are opened in response to count outputs from 1 to nt of the receiving side n-ary counter to pass the time-division single data applied to the data input terminal to separate and extract n pieces of data. Since the transmitter includes a receiving circuit having a receiving side gate, the number of wiring between the transmitting circuit and the receiving circuit can be reduced relative to the number of data to be transmitted, thereby facilitating construction.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の情報伝送装置のプCf9り図、第2図は
この発明の一実施例の情報伝送装置のブロック図、第3
図囚〜(6)はその各部の波形図である。 P・・・パルス発生回路、CT−・・送信側n進カウン
タ、GT工〜GTn・・・送信側アンドゲート、■、・
・・クロック出力端子、TT、−・・データ出力亀子、
TR工・・・クロ噌り入力端子、TR2・・・データ入
力端子、CR・・・受信側n進カウンタ、 GR工〜G
Rn・・・受信側アンドゲート
FIG. 1 is a block diagram of a conventional information transmission device, FIG. 2 is a block diagram of an information transmission device according to an embodiment of the present invention, and FIG.
Figures (6) to (6) are waveform diagrams of each part. P...Pulse generation circuit, CT-...N-ary counter on the transmitting side, GT engineering~GTn...AND gate on the transmitting side, ■, ・
・・Clock output terminal, TT, −・・Data output terminal,
TR engineering...Cross input terminal, TR2...Data input terminal, CR...N-ary counter on receiving side, GR engineering~G
Rn...Receiving side AND gate

Claims (1)

【特許請求の範囲】[Claims] 送信指令信号にもとづいてりOvクパルスを発生するパ
ルス発生回路と、このパルス発生回路のりc19クパル
スをカウントする送信側n進カウンタ(aは2以上の整
数)と、この送信側鶴進カウンタのlからntでのカウ
ント出力にそれぞれ応答して開くことによりn個のデー
タをそれぞれ通過させるn個の送信側ゲートと、前起パ
ルス発生回路Oクロックパルスを出力するりcI−yり
出力端子と−前6n個の送信側ゲートの出力を合成ふて
時分割3重データを出力するデータ出力端子とを有する
送信回路と、前記クロック出力端子よりりa!夕線を通
してクロックパルスが入力されるりaツタ入力端子と、
前記データ出力端子よタデータ線を通して時分割3重デ
ータが入力されるデータ入力端子と、前記クロック入力
端子に与えられ友タロ雫りパルスtカウントする受信l
In進カウンタと、この受信側n進カウンタのlからn
までのカラン)出力にそれぞれ応答して開くことくより
前記データ入力端子に与えられ良時分割n重データを通
過させてU個のデータを分離抽出する1個の受信側ゲー
トとを有する受信回路とを備えた情報伝送装置。
A pulse generating circuit that generates Ov pulses based on the transmission command signal, a transmitting n-ary counter (a is an integer of 2 or more) that counts the ripple pulses of this pulse generating circuit, and l of this transmitting side n transmitting side gates that respectively open in response to count outputs from nt to allow n pieces of data to pass through, and a pre-EM pulse generating circuit that outputs a clock pulse or cI-y output terminal and - A transmitting circuit having a data output terminal for synthesizing the outputs of the previous 6n transmitting side gates and outputting time-division triplex data, and a! A clock pulse is input through the evening wire, and an ivy input terminal;
The data output terminal has a data input terminal into which time-division triple data is input through the data line, and the reception l which counts the falling pulses given to the clock input terminal.
l to n of the in-ary counter and the n-ary counter on the receiving side
a receiving circuit having one receiving side gate which opens in response to each of the outputs (up to 1) and separates and extracts U pieces of data by passing the good time division n-fold data applied to the data input terminal; An information transmission device equipped with.
JP12856881A 1981-08-14 1981-08-14 Information transmitter Pending JPS5829234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12856881A JPS5829234A (en) 1981-08-14 1981-08-14 Information transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12856881A JPS5829234A (en) 1981-08-14 1981-08-14 Information transmitter

Publications (1)

Publication Number Publication Date
JPS5829234A true JPS5829234A (en) 1983-02-21

Family

ID=14987968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12856881A Pending JPS5829234A (en) 1981-08-14 1981-08-14 Information transmitter

Country Status (1)

Country Link
JP (1) JPS5829234A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172849A (en) * 1983-03-22 1984-09-29 Fujitsu Ltd Multiplexing circuit
JPS6330034A (en) * 1986-07-23 1988-02-08 Nec Corp Multiplexing circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172849A (en) * 1983-03-22 1984-09-29 Fujitsu Ltd Multiplexing circuit
JPS6331979B2 (en) * 1983-03-22 1988-06-28 Fujitsu Ltd
JPS6330034A (en) * 1986-07-23 1988-02-08 Nec Corp Multiplexing circuit

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