SU1605245A1 - Computer to sensors interface - Google Patents

Abstract

The invention relates to computing technology and is intended for automated systems for group control of technological devices (manipulators, accumulators, etc.) in real time, especially when there are a large number of objects (sensors) to be controlled and monitored remotely from information systems. control computer. The aim of the invention is to reduce equipment. The device contains a group of pulse shapers, a multiplexer, an OR element, a trigger, a group of registers, a receiver, a decoder, a transmitter, a counter. The device transmits information and control signals to an object remote from the computer, provides data transmission and with the simultaneous operation of several sensors. 2 hp f-ly, 3 ill.

Description

The invention relates to computing and is intended for automated systems for group control of technological processes, devices (manipulators, accumulators, etc.) in real time.

The purpose of the invention is to reduce equipment.

Figure 1 presents the block diagram of the device; figure 2 - diagram of the transmitter; on fig.Z - diagram of the receiver.

The device for interfacing the computer with sensors (Fig 1) contains a group of pulse formers 1, multiplexer 2, element OR 3, trigger 4, group of registers 5, delay element 6, receiver 7,

a decoder 8, a transmitter 9 and a counter 10,

The transmitter 9 (FIG. 2) contains a pulse generator 11, a counter 12, a trigger 13, an AND 14 element, a pulse shaper 15, a shift register 16, an AND 17 element, an interlock unit 18, an OR 19 element, a parity check node 20.

Receiver 7 (FIG. 3) contains a pulse generator 21, a counter 22, a trigger 23, a pulse former 24, an AND block 25, an interlock unit 26, a shift register 27, and a parity check node 28.

The device works as follows

The operation of any sensor causes the occurrence of a voltage gradient05

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, or at the input of the former of the group of pulse shapers 1. The latter generates a pulse of short duration, which passes through the element OR 3 to the trigger 4. The high potential from the output of the trigger 4 turns on the transmitter 9, which converts the signals from multiplexer 2 and counter 10 into a serial code arriving at the output of the device communication with a computer. In addition, the transmitter 9 generates one starting pulse and two stop pulses.

During the transmission of a message (byte) or at the moment of transmitting stop bits, the transmitter 9 generates a signal arriving at counter 10, changes its state and the state associated with counter 10 of multiplexer 2. As a result, all inputs are connected to the inputs of transmitter 9 devices. Since the transmitter 9 operates continuously, the state of the signals from all the K inputs of the device are sequentially, in groups, transmitted to the computer.

As soon as information from the device (from the sensors) is entered into the computer interface, the requirement for processor maintenance is automatically established. The processor analyzes the received data (sensor group code and its status, e), and, if required, generates a control action, which also causes this interface.

Since the cycle time for a processor to access the interface is 200-300 times shorter than the transmission time of a byte, the processor manages to interrogate and output the response information to several interfaces or other computer devices before the data about the next sensor group is received.

A control command formed by the processor is provided to the interface that transmits the data of the computer from the computer in the serial link in the same way as the transmitter 9.

The receiver 7 of the device on the second line of communication provides reception of information from the computer, converting it into a parallel code and transmitting it to the inputs of all registers 5 and to the inputs of the decoder 8. At the moment of reception by the receiver. 7, the reception end signal (the moment of receiving the stop bits) received at the control input of the decoder 8, the latter outputs a write signal to the input of the corresponding register of register group 5, in which the received information is written. As a result, the signals used to control the object are changed at the corresponding outputs of the register group 5. Another output of a group of registers 5 is connected to the input of delay element 6 and is used to control the operation of transmitter 9 in the following cases.

Firstly, to stop the cyclical operation of the transmitter 9. After being received by the processor, informing about the state of all inputs (sensors), the computer generates, at the additional output of the group of registers 5, a signal drop from a high level to a low, 5 which arrives at element 6 delay. The latter delays this signal by the time required to transmit data from all inputs (the delay time is counted from the moment the sensor last triggered) and resets trigger 4, which stops the operation of transmitter 9.

Secondly, when an ESH is requested to interrogate device inputs. In this case, the computer sets to 35 the same output of a group of registers 5 a high level of the signal, which arrives at the second control input of the transmitter 9. The latter starts transmitting data sequentially, in groups, to the computer until the signal is removed to its control level entrances.

The transmitter 9 operates as follows. The start signal (logical 1) is fed to one of the control inputs and through element OR 19 element AND 14 starts the pulse shaper 15. The logical signal O from the inverse output of the flip-flop 13 indicates the output of data to the communication line and prohibits the passage of the control signal (trigger) through the cell. ment And 14. After the data is output to the communication line, trigger 13 is reset by 55 counter and inverse output permits the trigger signal to pass through element 14. 14. The impulse from the driver 15 is sent to the leading edge again

40

triggers the trigger .13 and simultaneously loads into the register 16 data from the information inputs of the transmitter 9, start and stop signals, as well as a signal from the output of the parity control node 20. For this, the signal from the output of the parity check node 20 is generated based on the signals from the information inputs, and ensures the formation of a message on the communication line, for example, with an even number of logical 1 signals.

The trigger 13 is set to the leading edge of the signal from the driver 15 to enable the counter 12 and the output of information (the start bit) through the element 17 and the output unit 18 to the communication line with the computer. After every 16 clock pulses from the generator .11, which corresponds to the duration of one bit, the counter 12 outputs to the register 16 shift signals, providing a consistent output of information from the shift register 16 to the communication line. After counting the number of bits corresponding to the desired parcel, counter 12 causes the signal to reset trigger 13, which prohibits the operation of counter 12 and allows preparation for the transfer of the next byte of information (subject to high level signals at one of the inputs of transmitter 9). Since the falling edge of the signal from the driver 15 pulses goes to the counter 10 and puts it into the next state, the 8-n inputs of the transmitter 9 are connected to other inputs of the device. At the n inputs of the transmitter 9, the information also changes. Thus, in the next cycle, a byte of data about the next group of sensors is generated and transmitted.

Receiver 7 operates as follows. When the start bit arrives from the computer from the computer (it arrives in a logical way) and passes it through block 26, which ensures the matching of signal levels and galvanic isolation, the counter 22 (reception synchronizer) is turned on. After counting the counter 22 time interval equal to half of the bit, it resets the trigger 23 (the discriminator of the duration of the start bit) and simultaneously produces

input information in the shift register 27, coming from block 26.

If the duration of the input signal is less than half the bit length, the counter 22 does not reset trigger 23. Thus, the start bit is susceptible from possible interference in the communication line of the device with the computer.

After resetting the flip-flop 23, the latter allows further operation of the counter 22, regardless of the input signal level, and the receiver 7 receives any parcel. Next, the counter 22 counts the number of shifts, for example, 11 shift pulses (start bit, 8 data bits, 2 stop bits) or 12 shift pulses (when a parity bit is added), and sets a logical 1 signal at the output of the trigger 23. The latter resets the counter 22 and starts shaper 24. A 14 pulse from shaper 24 passes through I 25 element to the control output of the receiver in the event of the presence of permitting signals at the remaining inputs of this element coming from register 27 (stop bits) and parity control node 28 (confirmation and the received spreading). The control signal of the receiver 7, having passed the element 25, is fed through the decoder 8 of the device and ensures the recording of the received information into the register of the group of registers 5 selected by the decoder 8.

Claims (3)

1. A device for interfacing a computer with sensors containing a group of im-. pulses, multiplexer, OR element, trigger and register group, the input device group of the sensor interface is connected to the multiplexer information input group and the group of pulse formers, the outputs of which are connected to the inputs of the OR element, the output of which is connected to a single trigger input, The group register outputs are a group of outputs of the device for interfacing with sensors, characterized in that, in order to reduce the equipment, the device contains a delay element, a receiver, a decoder, a counter and a transmitter, the receiver's output group is connected to the information input groups of the register registers, the clock inputs of which are connected to the outputs of the decoder, the control input and the group of the formation inputs of which are connected respectively to the output and the output outputs of the receiver, whose inputs are the inputs of the device for interfacing with the computer, the multiplexer output group and the counter output group are connected via the corresponding INSTALLATION OR to the transmitter input group, the first control whose input is connected to the trigger output, the reset input of which is connected to the output of the delay element, the first and second inputs of which are connected to the output of the last group register and to the output of the OR element, respectively, the second control input of the transmitter is connected to the output of the last group register, The transmitter output group is a group of outputs of the device for interface with a computer, the transmitter output is connected to the counter input of the counter, the group of outputs of which is connected to the group of address inputs of the multi typlexer. 2. The device according to claim 1, characterized in that the receiver contains a decoupling unit, a counter, a pulse generator, a trigger, a pulse shaper, an AND element, a parity check node and a shift register, the receiver input group being connected to the input group of ki, whose output is connected to the resolution enable inputs of the counter and shift register, the data outputs of the shift register are connected to a group of inputs of the definition control node and is a group of receiver outputs whose output is connected to the output of the And element, the first and second The inputs of which are connected to the first and second informational outputs of the shift register, the third informational output of which is connected to the input of the control unit . Q 5 2 25 Q . 35 50 the output of the last bit of the counter is connected to the shift input of the shift register and to a single trigger input, the output of which is connected to the reset input of the counter and to the input of the pulse former, the output of which is connected to the third input of the And element, the fourth input of which is connected to the output of the parity check node , the overflow output of the counter is connected to the reset input of the trigger, the output of the pulse generator is connected to the counting input of the counter. 3. The device according to claim 1, characterized in that the transmitter contains a counter, a pulse generator, a parity check node, a shift register, two AND elements, a junction block, a pulse shaper, an SHSh element and a trigger, the group of inputs of the transmitter connected to the node inputs parity check and with the group of inputs of the shift register, the overflow output of which is connected to the first BXOJ house of the first element AND, the output of which is connected to the input of the isolation unit, the outputs of which are the group of outputs of the transmitter, the first and second control inputs of which o are connected respectively to the first and second inputs of the OR element, the output of which is connected to the first input of the second element AND whose output is connected to the input of the pulse former, the output of which is connected to the single trigger input, to the output of the shift register, the shift input which is connected to the first output of the counter, the second output of which is connected to the reset input of the trigger, the direct output of which is connected to the enable input of the counter and to the second input of the first element And, the counting input etchika connected to the output of the pulse generator, the parity output node connected to the input shift register, the flip-flop inverse output coupled to a second input of the second element I. 1 FIG. g