SU1515369A2 - Device for converting pulse recurrence rate - Google Patents

Abstract

The invention relates to automation and can be used in digital synchronization systems of communication stations. The purpose of the invention is to expand the range of converted pulse frequency. The goal is achieved due to the fact that the device containing group 1 of counting triggers, driver 2, element OR 3, N-bit register 4, group 5 of N delay elements, group 6 of N gate elements, (L + 1) -discharge adder 7 with (N + 1) inputs, entered (L + 1) -discharge adder with N inputs and a key block, which allows you to organize an additional sub-band of the converted frequencies. 3 il.

Description

ate

ate

with

Oi (G

In their clothes

 go

-

The invention relates to automation and can be used in systems 1-p | frovnogo synchrotisation communication stannyh.

The aim of the invention is to expand the range of converted pulse frequencies.

Figure 1 presents the functional diagram of the device; 2 execution of a group of keys; FIG. 3 shows an example of connecting the adder to a group of triggers for the case when,.,

The device for converting the pulse frequency contains a group 1 of (N + L) series-connected triggers, a shaper of 2 pulses, this OR OR 3, N-bit register 4, group 5 of N delay elements 5.1-5.N, group 6 of N gating elements are 6.1-6.N, (L + 1) -disp dn1,1e adders 7 and 8 with N inputs, a group of 9 keys and 1 S1 of 10 control of the range of converted frequencies.

The group of 9 keys contains (L + 1) logical elements 2I 11.1-11. (L + and D-trigger 12.

Cha Conversion Device. - you follow the impulses of work: - the next one;

In the initial state, on the input bus of the digital control unit on the range control pin 10, there are signals O, and the tritters 1.1-l. () Of group 1 are trigger and the register 4 can be in an arbitrary state. Signal O with input

The range control bus 10 arrives at the first control input of the group 9 key-; and prohibits the passage of sipnal from ipfopma oksyx inputs of a group of 9 keys on its inputs.

8 as a result of the group outputs

9klyuch are signals O

With the arrival of the control of the pulse code, the pilot bus of the digital control or during I. 3, an impulse of the 1st signal is formed, setting the triggers 1 .1-1 to the single-dimensional state. (tJ +.) rpyimb 1 triggers and obiulki .ip M-rlzr lt s; 1 register 4. Formed scheds; , O at the outputs) of the regular register 4 block; 1 l; pt.1 6.1-6.N group 6 elrmeito c i poonpoi amui, 1a exits to groups i -j.n g meites CTpofiiipo-- vani also set a1 L1 gp (G JAN1Ts cuipa.ii

ten

20

s s 10 1)

- 30 e - 35 d25

one

s

about 3 s

515369

A. These signals are fed to the inputs of the (L + 1) -discharge adder 7, and 5 signals O from the output of the group of 9 keys are fed to its (N4l) -ft input. At the output (L + D-ro bit of the sum of adder 7, the O signal is generated. At the time interval TJQA defined by the .5.1-5.N elements of the group 5 delay elements, the new value of the control code is entered into the N-bit register 4, the decimal equivalent of which determines the value of the pulse frequency of the output sequence. When the first trigger 1.1 of group 1 of the first pulse of the input sequence arrives at the input, the inverse outputs of the trigger 1.1-1 are generated at the inverse outputs (1 + 1). These signals from the inverse outputs triggers g The groups 1 of the flip-flops are fed to the inputs of the adder 8 and to the informational inputs of the group 6 of the gates 6.1-6. You "In accordance with the value of the control code Z on the output of the N-bit register 4, the gates 6.1-6 will be opened. N group 6 strobe elements. As a result, the corresponding (L + 1) -digit outputs of group 1 of the flip-flops will be connected to the inputs of the adder 7 and the output will change at the output of the (L + +1) -th bit of the sum of the adder 7 from level O to 1. At the same time, the driver 2 pulses at its output generating a first output pulse sequence repetition frequency-converted. With the arrival at the input of group 1 of triggers of successive pulses of the input sequence, linearly decreasing binary codes are formed at the inverse (L + 1) -size i-x (i 1, N) outputs of group 1 of triggers, the rate of change of which is proportional to the corresponding converted pulse frequency. These codes, through the corresponding elements of the group of 6 gating elements, arrive at the corresponding inputs of the (L-f 1) -discharge adder 7, which summarize the codes modulo. Depending on the value of the control code, a sequence of pulses is formed at the output of the (L + 1) -discharge adder 7, the frequency of which is

40

45

50

55

proportional to the decimal equivalent of the binary control code received on the digital control input bus. The shaper 2 pulses at its output generates standard pulses each time the signal at the output of the adder 7 changes from level O to 1,

When a signal 1 arrives at the input bus 10 controlling the range 1, the next pulse of the input sequence gives permission for the signal from the output of the adder 8 to (N + 1) -A input of the adder 7, Depending on the value of the control code to the N inputs of the adder 7 through the elements 6.1 The -6.N group of 6 gates receives linearly decreasing binary codes, the values of which change over a given period of time at different rates. The specified time interval is determined by the frequency value of the input pulse sequence, the total bit size of group 1 of N and L flip-flops and is defined as t) (2 As a result of summation of binary codes from the outputs of group 6 of gates to the inputs of adder 7, with linearly decreasing binary the code arriving at (H + 1) -th input of adder 7, at (L + 1) -M output of the sum of adder 7, a pulse sequence is formed, the pulse frequency of which depends on the result of the sum of the linearly decreasing binary code (N + 1) -M adder input

7 and with the set register 4 and the route 6 of the gating elements by the combination of linearly decreasing binary codes at the N inputs of the adder 7. From the output of the driver, 2 pulses per

output of the device receives initial pulses of the decoded sequence when the sum of the 7 signal from the level O to 1 is changed at the (L41) th output.

Group 9 of the keys works as follows (figure 2).

In the initial state, the trigger 12 is in the zero state, in which the O signal is present at its direct output. The initial state of the trigger 12 can be ensured, for example, by applying to the R-input of a short-term trigger.

five

0

five

0

five

0

five

0

five

pulse, the formation of which is carried out with the help of a differentiating circuit connected between the R input of a trigger and a source of power voltages. The signal from the direct trigger output goes to the combined first inputs of elements 2I 11.1-11. (L + 1) and prohibits the passage of signals in the form of 1, arriving at their second inputs, or the output of the block. As a result, O. signals are present at the output of group 9 of keys. When a group of 9 keys arrives at the first control input, and consequently, information O of the trigger 12 of the signal O about the next impulse of the input sequence arriving at the second control input of the block and further to the C input of the trigger 12, the initial state of the trigger 12 is confirmed. At the same time, the output of the block in all (L + 1) bits is set to O levels, which corresponds to a zero value of the output binary code at the output of the block. When a signal in the form of level 1 arrives at the first control, the next impulse of the input sequence sets the trigger 12 to a single state in which the signal 1 is generated at its forward output. This signal arrives at the combined first inputs of the elements 2I 11.1-11. +1). As a result, the signals at the second inputs of elements 2I 11.1-11. (L + 1) in the form of O or 1 are output to a group of 9 keys, i.e. this ensures the transmission of signals from the information inputs of the block to its output,

/ Thus, depending on the type of signal at the first control input of the block, the latter provides for the transmission or prohibition of the passage of a linearly killing binary code arriving at the information input.

block.

I.

Due to the fact that the generated output sequence is fed to the input of the pulse former from the senior (L + 1) -ro bit sum of the adder, the pulse frequency at the output of the device when the binary codes are received for each i-th separately connected corresponding input of the adder to the corresponding the output of the group of triggers will be determined by the expression

f, -

fa, 24 ---)

;

(one)

Where

L I

i 1, N is the group number (L + 1) —digital outputs of the trigger group; the number of additionally connected triggers in the group; pulse frequency of the input convertible pulse sequence,

In accordance with the value of the control code Z, a group of gates connects to the inputs of the adder 7 separate i-e outputs of group 1 of triggers and, therefore, at the output of the adder 7 a pulse sequence is formed, the pulse frequency of which will be determined by the expression

feuK Z-f; i. f., (2)

where sg; O or 1 is the i-ro value of the control code. Taking into account the correction of the output frequency value by the adder 8

OUT

N

, f. +

. r fex (1),

(3)

5 where J o, 1, depending on the bus condition, setting the frequency band to be converted.

- ten

Claims (1)

Formula isobteni Pulse frequency conversion device according to auth. No. 1387199, characterized in that, in order to expand the range of converted pulse-following frequencies, a second (L + +1) -disk total adder with N inputs is introduced, and the first (L + 1) -discharge adder is provided with an additional (N + 1) -M input, a block of keys, the first and second control inputs of which are the range reference bus and the input bus, respectively, the information inputs are connected to the corresponding outputs of the second (L + 1) -disc adder with N inputs, and the inputs to the corresponding N +1 inputs of the first. (L + 1) -discharge adder with N + 1 inputs, inverse outputs from i-ro to (1 + b) -th counting flip-flops are connected to the corresponding i-th inputs of the second (L + 1) -disc adder with N inputs, and that is 1, N. v 2.2 ) FIG. 2