JPH104393A - Data compression and expansion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a first-in first-out(FIFO) buffer to be placed corresponding to the multiplexed number to a transmitter and receiver side for compression/multiplexing of transmission data and demultiplexing/expanding of received data in a digital mobile communication operated by the time division multiplex(TDMA) system. SOLUTION: A selector 2 receives a TDMA input of multiplexed data, selects and outputs data in a timing sequence designated by an address timing signal generating section 3 and writes the data to a different storage area of a RAM 1 from each multiplexed component and reads the data and sends the data as a traffic data output. Moreover, the selector 2 receives traffic data to be multiplexed in time division after demultiplexing/expansion in a timing sequence designated by the address timing signal generating section 3, writes the data to different storage area of the RAM 1 an reads the data and sends the data as the TDMA data output of the multiplexed data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression / decompression device, and more particularly to a method for transmitting a plurality of data transmitted from a plurality of output devices used in a digital mobile communication system operated in a TDMA (time division multiple access) system on a TDMA time slot. The present invention relates to a data compression / expansion apparatus for compressing / multiplexing data and separating / expanding a plurality of data on a TDMA time slot to a plurality of input devices used in digital mobile communication.

[0002]

2. Description of the Related Art When performing TDMA data transmission,
Data from a plurality of output devices is compressed / multiplexed and transmitted on a TDMA time slot. Also, data on the TDMA time slot is separated / expanded and sent to a plurality of input devices. To realize these, a demultiplexing circuit and a FIFO (First-In First-Out) buffer for performing compression / expansion are provided to perform compression / multiplexing and demultiplexing / expansion.

FIG. 3 is a block diagram showing a configuration of a conventional data compression / decompression device. In FIG. 3, 201 is the TDM
TDMA data input on slot A, 202: demultiplexer for demultiplexing and decompression, 203: timing generation circuit for generating compression / multiplexing and demultiplexing / decompression timing signals, 204 to 207 and 216 to 219, FIFOs respectively. Buffers (1) to (4) and FIFO buffer
(5) to (8), 208 to 211 are traffic data outputs, 212
215 is a traffic data input to be compressed / multiplexed; 220 is a multiplexer for performing compression and multiplexing;
Reference numeral 1 denotes a TDMA data output to be transmitted onto a TDMA slot, and 222 denotes a control unit for controlling the entire operation. The operation of the conventional data compression / decompression device will be described below.

[0004] Compressed / multiplexed T on time slots
DMA data input 201 is input to demultiplexer 202. The demultiplexer 202 is a timing generation circuit
The multiplexed data is separated at the timing of the input timing signal 2031 that specifies the timing of the TDMA input generated at 203, and the corresponding FIFO buffers (1) to (4) 204 to 20
Output data to 7.

In this case, the compressed / multiplexed TDMA data input is made up of four consecutive data strings transmitted over four time slots in a predetermined repetition in order to ensure reliable transmission of the data. Since a stream is taken as an example, the number of FIFO buffers is also four, but in general, the number of time slots occupied repeatedly and therefore the number of corresponding FIFO buffers can be arbitrarily set.

[0006] FIFO buffers (1) to (4) 204 to 207
Outputs traffic data outputs 208 to 211 at the timing of the traffic output timing signal 2032 generated by the timing generation circuit 203.

On the other hand, traffic data inputs 212 to 215 to be compressed / multiplexed on a time slot are input to FIFO buffers (5) to (8) 216 to 219. The FIFO buffers (5) to (8) 216 to 219
The data is output to the multiplexer 220 at the timing of the traffic input timing signal 2033 generated in (3).

The multiplexer 220 compresses / multiplexes the input data at the timing of the output timing signal 2034 for designating the timing of the TDMA output generated by the timing generation circuit 203, and outputs the TDMA data output 221.
The control unit 222 incorporates a control program and controls the entire operation.

FIG. 4 is an explanatory diagram schematically showing conventional separation / expansion and compression / multiplexing of multiplexed data. FIG.
(A) shows separation / expansion of multiplexed data, and (b) of FIG. 4 shows compression / multiplexing into multiplexed data. In the case of separation / expansion of multiplexed data, TDMA is used as shown in FIG.
A plurality of data multiplexed on a time slot, in this case, data T1, T
2, a TDMA data input 201, represented as a T3 and T4 bit stream, is decompressed /
Buffer (1) input, FIFO buffer (2) input, FIFO
O buffer (3) input and FIFO buffer (4) indicate that they are temporarily stored in the respective FIFO buffers as inputs.

In the case of compression / multiplexing to multiplexed data, a FIFO buffer is used as shown in FIG.
(5) Output, FIFO buffer (6) output, FIFO buffer (7) output, and FIFO buffer (8) compression / multiplexing are performed to obtain a TDMA data output 221 as a multiplexed bit stream. Is shown.
Thus, compression / multiplexing of data on the time slot and separation / expansion of data on the time slot are executed.

[0011]

However, in the above-mentioned conventional data compression / expansion apparatus, since the input / output timing of each FIFO buffer is different, a FIFO buffer of TDMA multiplexing number × 2 is required for transmission and reception.
There is a problem that an increase in the circuit scale inevitably leads to an increase in mounting space and an increase in price.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to reduce the compression / compression of a plurality of input / output devices and TDMA slots without using a complicated circuit configuration.
An object of the present invention is to provide a data compression / decompression device for performing multiplexing and demultiplexing / decompression.

[0013]

The present invention has the following means in order to achieve the above object. That is, a first configuration of the present invention relating to a data compression / expansion device is to compress / multiplex data transmitted from a plurality of output devices in a TDMA time slot in digital mobile communication operated by the TDMA method, A data compression / expansion apparatus characterized by separating / expanding and supplying the data to a plurality of input devices corresponding to the plurality of output devices in digital mobile communication. Each configuration is provided. (A) A first write / read for writing and reading a plurality of data obtained by separating / expanding a TDMA data input compressed / multiplexed on a TDMA time slot to and from a predetermined storage area, respectively, A storage medium for executing a second write / read in a time-division manner for writing and reading a plurality of traffic data inputs to be compressed / multiplexed in a time zone different from the write / read in a predetermined storage area, respectively (b) TDMA time slot An externally provided TDM that receives the compressed / multiplexed TDMA data input above
Under the control of the A input timing signal, a plurality of multiplexed components are sequentially selected and output to perform multiplexing / demultiplexing, thereby ensuring the first writing / reading to be written to the storage medium, and a traffic output provided from the outside. A first selection process for outputting the multiplexed component read from the storage medium as traffic data in a predetermined timing sequence under control of a timing signal;
A plurality of traffic data inputs to be compressed / multiplexed on an MA time slot are received, and the first write / read operation is performed on a predetermined storage area of the storage medium under the control of an externally provided traffic input timing signal. Is time-divisionally written and TD provided from outside
A second selection process for ensuring the second write / read to be read out from the storage medium under the control of the MA output timing signal and output as a compressed / multiplexed TDMA output by outputting in a predetermined timing sequence. (C) the TDMA input timing signal, the traffic output timing signal, the traffic input timing signal, and the TDMA output timing signal in the first and second writing / reading to / from the storage medium. An address timing signal generating section for generating an address timing signal including a timing designation of an address access to a predetermined storage area; (d) an operation of the storage medium, the selector, and the address timing signal generating section incorporating a control program; Control A control unit for

According to a second configuration of the present invention, in the first configuration, the storage medium is a RAM.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In digital mobile communications operated by the TDMA system, a plurality of data transmitted from a plurality of output devices are compressed / multiplexed on a TDMA time slot, and a plurality of data are transmitted on a TDMA time slot. Is separated / expanded and supplied to a plurality of input devices.

A data compression / expansion device performs such compression / multiplexing and demultiplexing / expansion of a plurality of data. In a conventional data compression / expansion apparatus, a plurality of data obtained by demultiplexing / decompressing multiplexed data on an input TDMA time slot by a demultiplexer are output via individual FIFO buffers, and should be compressed / multiplexed. A plurality of data are also compressed / multiplexed by a multiplexer via respective FIFO buffers.

Therefore, in the conventional data compression / decompression device,
A FIFO buffer corresponding to the number of multiplexes is required on the transmission and reception sides, and an increase in the circuit scale is inevitable, resulting in an increase in mounting space and an increase in cost.

In the present invention, in order to improve the above-mentioned problems, basically, compression / multiplexing of a plurality of data corresponding to the number of multiplexing in digital mobile communication operated by the TDMA system and separation / decompression thereof are performed. Is executed by time-division use of one storage medium, and R is used as a storage medium.
Separation / expansion is performed by writing and reading multiplexed data in the AM at a predetermined address different for each multiplexed component in a predetermined timing sequence. Are written and read in a predetermined sequence to perform compression / multiplexing.

In this case, the operation of ensuring the timing sequence of writing / reading to / from the RAM is shared by a selector operation for executing the selective output of data under the control of a predetermined timing signal.
An embodiment of the present invention is to generate an address timing signal for setting the timing of the address access of M. Therefore, it is not necessary to provide a plurality of FIFO buffers and related circuits corresponding to the number of multiplexes, and the compression / compression of an extremely simple configuration is achieved. Multiplexing and separation / decompression are realized.

[0020]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a data compression / decompression device according to an embodiment of the present invention. The data compression / expansion apparatus shown in FIG. 1 stores data obtained by separating / expanding a compressed / multiplexed TDMA data input or data to be compressed / multiplexed in a predetermined storage area in a time-division manner with respect to each other. RAM1 as a medium, RAM1
An address timing signal generator 3 for transmitting various address timing signals for setting a write / read timing sequence together with address designation information in time-division use, and controlling various address timing signals generated by the address timing signal generator 3. RAM while receiving
1 is provided with a selector 2 for executing writing / reading for 1 to perform compression / multiplexing of a plurality of data and separation / expansion of multiplexed data, and a control unit 4 for controlling the entire operation sequence.

Next, the operation of this embodiment will be described.
First, the separation / decompression processing of the input multiplexed data will be described with reference to FIG. FIG. 2 is an explanatory diagram schematically showing separation / expansion and compression / multiplexing of multiplexed data in the embodiment of FIG. FIG. 2A shows the case where the number of multiplexing is set to 4 for the demultiplexing / expansion, and FIG. 2B shows the case where the number of multiplexing is set to 4 for the compression / multiplexing.

First, compression / multiplexing will be described. In the case of compression / multiplexing, a TDMA data input 101 obtained by multiplexing a plurality of multiplexed data, for example, four data corresponding to a multiplex number of 4 on a TDMA time slot is provided by a selector 2.
Is input to The selector 2 receives the TDMA input timing signal 10 supplied from the address timing signal generator 3.
T of the multiplexed data based on the timing sequence of 3.
DMA data input 101 is separated by selective output processing,
Each is written to a predetermined storage area of the RAM 1. This writing is performed under the control of the control unit 4.

The TDMA data input 10 shown in FIG.
In 1, data T5, T6, T7 and T8 as multiplexed components are sequentially written at predetermined addresses in the RAM 1. Each component data of the multiplexed data written in this way is read out sequentially from the RAM 1 in a predetermined sequence by the traffic data output timing signal 104 and supplied to the selector 2.

The selector 2 selects and outputs data sequentially read from the RAM 1, outputs the data in a predetermined output sequence, and outputs traffic data 107, 108, 109 and 11
Set to 0. FIG. 2A shows T5, T6, T7 and T5.
Reference numeral 8 denotes traffic data that is successively separated and output. The output of such traffic data by the selector 2 is also performed under the control of the control unit 4.

Next, compression / multiplexing will be described. This compression / multiplexing is also performed in a time-division manner with the separation / expansion processing under the control of the control unit 4 as follows. The selector 2 has a plurality of traffic data to be multiplexed, in this case, the same four traffic data inputs 111, 112, 11 as in the case of separation / expansion.
3 and 114 are used as traffic data input timing signals 105 supplied from the address timing signal generator 3.
While the data is selected and output in the timing sequence specified by, the data is written to a predetermined recording area of the RAM 1.
The writing to the RAM 1 and the reading from the writing / reading in separation / expansion are separated in time from the RAM 1
Is performed in a time-sharing manner.

The traffic data written in the RAM 1 is then read out in a timing sequence specified by the TDMA output timing signal 106 supplied from the address timing signal generator 3 and selectively output to establish diversification. , TDMA data output 102. FIG. 2B shows such a compression / multiplexing process.

Under the control of the control unit 4, the selection output function of the selector 2 and the various timing signals transmitted from the address timing signal generation unit 3 for specifying the timing sequence for determining the processing pattern of the selection output of the selector 2 are used. By writing / reading to / from the RAM 1 in a time-division manner by separation / expansion and compression / multiplexing, a large number of F
Separation / decompression and compression / multiplexing that do not require an IFO buffer and its related circuits can be performed.

[0028]

As described above, according to the present invention, T
The compression / multiplexing of a plurality of data and the demultiplexing / decompression of multiplexed data in digital communication operated in the DMA system are performed by time division processing of writing / reading to / from a storage medium, and input / output of write / read data in the time division processing. By executing based on the temporal sequence control of the output,
This has the effect of realizing a data compression / decompression device having a remarkably simple configuration that does not require a plurality of FIFO buffers and associated circuits to be disposed on the transmission / reception side in accordance with the number of multiplexes.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data compression / decompression device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram schematically showing data separation / expansion and compression / multiplexing in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a conventional data compression / decompression device.

FIG. 4 is an explanatory diagram schematically showing separation / expansion and compression / multiplexing of data in FIG. 3;

[Explanation of symbols]

 Reference Signs List 1 RAM 2 selector 3 address timing signal generator 4 controller

Claims (2)

[Claims] 1. A digital mobile communication system operating in a TDMA system, comprising: a plurality of output devices for compressing / multiplexing data transmitted from a plurality of output devices on a TDMA time slot; A data compression / decompression device for separating / decompressing and supplying to a plurality of input devices corresponding to the plurality of output devices in mobile communication. (A) A first write / read for writing and reading a plurality of data obtained by separating / expanding a TDMA data input compressed / multiplexed on a TDMA time slot to and from a predetermined storage area, respectively, A storage medium for executing a second write / read in a time-division manner for writing and reading a plurality of traffic data inputs to be compressed / multiplexed in a time zone different from the write / read in a predetermined storage area, respectively (b) TDMA time slot An externally provided TDM that receives the compressed / multiplexed TDMA data input above
Under the control of the A input timing signal, a plurality of multiplexed components are sequentially selected and output to perform multiplexing / demultiplexing, thereby ensuring the first writing / reading to be written to the storage medium, and a traffic output provided from the outside. A first selection process for outputting the multiplexed component read from the storage medium as traffic data in a predetermined timing sequence under control of a timing signal;
A plurality of traffic data inputs to be compressed / multiplexed on an MA time slot are received, and the first write / read operation is performed on a predetermined storage area of the storage medium under the control of an externally provided traffic input timing signal. Is time-divisionally written and TD provided from outside
A second selection process for ensuring the second write / read to be read out from the storage medium under the control of the MA output timing signal and output as a compressed / multiplexed TDMA output by outputting in a predetermined timing sequence. (C) the TDMA input timing signal, the traffic output timing signal, the traffic input timing signal, and the TDMA output timing signal in the first and second writing / reading to / from the storage medium. An address timing signal generating section for generating an address timing signal including a timing designation of an address access to a predetermined storage area; (d) an operation of the storage medium, the selector, and the address timing signal generating section incorporating a control program; Control A control unit for 2. The data compression / decompression device according to claim 1, wherein said storage medium is configured as a RAM.