JPH0973388A - Data converting device with priority - Google Patents

Abstract

PROBLEM TO BE SOLVED: To multiplex data of arbitrary length into a limited part like a header part by storing a memory with arriving parallel data of arbitrary length, and reading them out in predetermined order and outputting them as serial data. SOLUTION: A multiplexing circuit 1 inputs transmitted data A from an input terminal 3 and information data C outputted from a data control circuit 2 and multiplexes the information data C into the header part of each frame. A data control circuit 2 stores a previously allocated memory with arriving parallel data E1, E2Rv of arbitrary length and monitors whether or not the data are stored in the memory. When the data are stored in the memory, the data are read out of the memory in predetermined order (in preferential order), and outputs them as serial data and deletes the data having being sent from the memory. The data of the arbitrary data when stored in the memory are adjusted to specific data length and they are read out sequentially and transmitted as the serial data, so that the data are multiplexed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system for prioritizing incoming parallel data of arbitrary length and outputting it as serial data, and more particularly to a transmission having a frame format composed of a header section and a data section. In the method, the present invention relates to a technique of multiplexing information other than transmission data in a header part and transmitting the same.

[0002]

2. Description of the Related Art When data is multiplexed and transmitted by using a limited portion such as a header portion in a frame,
Since the data transmission capacity of the header part is not so large (generally less than several bits), the type of information to be transmitted is limited in advance, and the limited information is converted into a bit pattern with a fixed length of several bits. Generally, a method of multiplexing and transmitting with the bit pattern is adopted.

[0003]

However, in the conventional technique, there is a problem that only the data assumed in advance, that is, the information defined as the bit pattern can be transmitted, and
When the area to be multiplexed has a fixed length, there is a problem that a bit pattern composed of more bits must be prepared when transmitting other types of data.

In view of the above problems, an object of the present invention is to allow data having an arbitrary length to be multiplexed into a limited portion such as a header portion of transmission data, and various kinds of information. It is to provide a data conversion device capable of transmitting data.

[0005]

The prioritized data converter provided by the present invention stores first incoming parallel data of arbitrary length in a pre-allocated memory, and data stored in the memory. Second means for monitoring whether or not the data is stored, and when the data is stored in the memory, the data is read from the memory in a predetermined order (priority order), output as serial data, and the reading is completed. And a third means for deleting the stored data from the memory. Further, when storing the parallel data of the arbitrary length in the memory, the data of the arbitrary length is stored after being adjusted to a predetermined data length, which is sequentially read out and transmitted as serial data to multiplex a predetermined area. Is further included. In addition, preferably, the area for multiplexing the serial data is the header portion of the transmission data including a header portion and a data portion.

[0006]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a prioritized data conversion device of the present invention. In FIG. 1, reference numeral 1 is a multiplexing circuit, to which the transmission data A from the input terminal 3 and the information data C output from the data control circuit 2 are input. The data of the transmission data A has a periodic frame structure including a header part and a data part, as shown in FIG. 3A and FIG. 3B showing the details thereof.

The multiplexing circuit 1 multiplexes the information data C output from the data control circuit 2 into the header portion of each frame. The timing of multiplexing is controlled by the control signal D input from the control signal input terminal 6. The multiplexed data is output as multiplexed data B from the output terminal 4.

FIG. 2 is a detailed configuration diagram of the data control circuit 2. The information data C output from the data control circuit 2 will be described with reference to FIG. The data control circuit 2 receives input data E1 to E input from the information input terminal 5.
A plurality of buffers Fl that temporarily hold n (n is a natural number)
Fn and a buffer read circuit 21 for reading the data held in each of the buffers F1 to Fn.

For the sake of convenience, the following description will be given assuming that the number of buffers is 3 and the priority of the buffers is "E>E2>E3". Data El to E3 are asynchronously input to the buffers Fl to F3. The buffer read circuit 21 constantly monitors the three buffers F1 to F3 and reads the data of the buffer to which the input has been made. The reading is always performed from the buffer having the higher priority, and the data stored in the buffer having the lower priority is on standby until the reading of the data being read is completed.
The data will be cleared when the reading is completed.
The next input data will be on standby.

FIG. 4 is a time chart showing a state in which the reading of the data E1 to E3 is controlled by the buffer control circuit 21. Referring to FIG. 4, first, the data E1-1 having the highest priority is read. Before this reading is completed, the next data E2-1 is input to the buffer F2. Therefore, the reading of the data E2-1 is started when the reading of the data E1-1 is completed. During this reading, the data E3-1 is input to the buffer F3, and the data E1-2 is input to the buffer F1. In such a case, the data E1-2 having the higher priority is read first, and the data E3 is read when the reading is completed.
-1 is read out. After that, under the same read control,
Information data C is output from the data control circuit 2.

FIG. 5 is a diagram showing the structure of the multiplexed data B output by the multiplexing of the transmission data A and the information data C by the multiplexing circuit 1 of FIG. Referring to FIG. 5, the data E1- is added to the header part of the first frame.
1 has data E2-1 (data E2-1 ', data E2-1''...) Multiplexed in the header of the next frame. Here, since the data E2-1 is larger than the area of the header part, it is also recorded in the header part of the next frame.
When all the data E2-1 is recorded, the next data E1-
2 (data E1-2 ′, data E1-2 ″ ...) Are recorded in the same manner.

Here, since the data E1 to E3 are data of arbitrary length, the delimiter of each data cannot be grasped on the receiving side. However, for example, by providing a data length adjusting circuit between the information input terminal 5 and the buffers F1 to F3 of FIG. 2 and additionally forming a variable length dummy bit (dummy portion) in the header portion, a multiple value of the bit in the header portion is formed. The lengths of the data E1 to E3 are adjusted so that As a result, the length of one data is always an integral multiple of the header area,
When the header part is expanded on the receiving side, if one header part has no meaning as data, the next header part is concatenated and expanded, or a dummy bit inserted in the header part is detected. Corresponds by reproducing the header section as one data delimiter.

FIG. 6 shows the procedure of buffer read control. To control the reading of data from each of the buffers F1 to F3, first,
It is confirmed whether or not the data is stored in the buffer F1 having the highest priority. If the data exists, the data is output. If the data is not in the buffer F1, the data reading process from the next buffer F2 is performed. Transfer (S1). Here, it is confirmed whether or not the data exists in the buffer F2, and if the data exists, the data is output.
The process moves to the data reading process of No. 3 (S2). Similarly, it is confirmed whether or not the data exists in the buffer F3, and if the data exists, the data is output.
The process returns to the data reading process from (S3). During this time, the information output from the data control circuit 2 is constantly monitored (S4),
When new data is stored in each of the buffers F1 to F3, the processes of S1 to S3 are repeated. When the data output is completed, the data stored in the corresponding buffer is deleted (S5).

Next, new data is read from the buffer based on the information monitored during the data output (S
6) If the reading is completed (S8), the read data is output (S8). The feature of the present invention is that variable-length data is prioritized and output as serial data, and there is no particular problem as to how the receiving side develops.

As described above, according to the present embodiment, a plurality of parallel data input to the data control circuit 2 with an arbitrary length are output as the serial information data C rearranged in the reading priority order. C can be easily multiplexed in the header part of the data A.

[0016]

As is apparent from the above description, by using the prioritized data conversion device of the present invention, data having an arbitrary length can be converted into a limited portion such as a header portion of transmission data. It becomes possible to multiplex, and the transmission path can be used more efficiently. Further, since it becomes possible to transmit more kinds of information than before, it is possible to expand the use of the header section.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a data control circuit according to the present embodiment.

FIG. 3 is an explanatory diagram showing a configuration example of transmission data A according to the present embodiment.

FIG. 4 is a block diagram showing data E by the buffer control circuit of the present embodiment.
The time chart which showed the state where reading of 1-E3 is controlled.

FIG. 5 is an explanatory diagram showing a configuration example of multiplexed data B output by the multiplexing of transmission data A and information data C by the multiplexing circuit of the present embodiment.

FIG. 6 is an explanatory diagram of a procedure of buffer read control according to the present embodiment.

[Explanation of symbols]

 1 Multiplexing Circuit 2 Data Control Circuit 3 Transmission Data Input Terminal 4 Multiplexing Data Output Terminal 5 Information Input Terminal 6 Control Signal Input Terminal 21 Buffer Reading Circuit A Transmission Data B Multiplexing Data C Information Data D Control Signal El to En Data Fl ~ Fn buffer

Claims (4)

[Claims] 1. A first means for storing incoming parallel data of arbitrary length in a pre-allocated memory, and a second means for monitoring whether or not the data is stored in the memory.
And a third means for reading data from the memory in a predetermined order and outputting as serial data when the data is stored in the memory, and for deleting the read data from the memory. A prioritized data conversion device having. 2. The method according to claim 1, further comprising means for adjusting the arbitrary-length data to a predetermined data length and storing it when storing the arbitrary-length parallel data in the memory. Prioritized data converter. 3. The prioritized data converter according to claim 1, wherein the predetermined data length is n times (n is a natural number) the area in which the serial data is multiplexed. 4. The area for multiplexing the serial data is the header portion of transmission data composed of a header portion and a data portion.
The data conversion device with priorities according to any one of 1.