JPS6394730A - Split multiplex packet signal decoding device - Google Patents

Abstract

PURPOSE:To minimize the increase in a storage circuit even if the number of stations is increased by using the storage circuit in common. CONSTITUTION:A detector 2 outputs detection information to a head address managing device 3. The head address management device 3, based on the information, supplies a head address to write a split packet signal into a storage circuit 1 to the 1st counter 4. When a packet end of a split packet sent from a station is reached, the detector 2 informs it to the head address managing device 3. Since the original packet signal is to be obtained by combining signals sent so far from the station, the head address managing device 3 sends the head addresses corresponding to the split packet signals stored so far with respect to the said station to the 2nd counter 5 sequentially in the stored order. The 2nd counter 5 sends the address signal of the 2nd counter area having the designated head addresses in the order of inputs to the storage circuit 1. The storage circuit 1 outputs the data included in each address sequentially from a terminal 1002.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a division multiplexed packet I-signal restoration device, and more particularly to a division multiplexed packet signal restoration device for restoring time division multiple accessed packet signals.

[Conventional technology]

Conventionally, packet signals are connected via time division in wireless communication (hereinafter referred to as r TDM A J < Time D).
ivisionMu! 1tiple Access)
A method of transmitting data using the following is being considered. This method is used for packet transmission using communication satellites.
Simultaneous transmission from multiple points is easy and highly effective, and can be achieved by providing a converter between a packet signal and a TDMA signal as a transmitter/receiver.

FIG. 5 is a block diagram of a typical conventional division multiplexed packet signal restoration device constituting the above-mentioned conversion device. . . . Ions are prepared and the time division multiplexed signals are separated and stored for each transmitting station, and each storage circuit 101, 102, . . . Ions are divided and sent at the transmitting station. It is designed to output when the divided packets are completed.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional division multiplex packet signal restoration device, the memory capacity of each storage circuit is limited to the maximum packet length while the maximum packet length is Amount x number of stations −−−−−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−−−−−−< 1
), and since the memory capacity at each station is multiplied by the number of stations in equation (1), it has the problem that it increases at an accelerated pace as the number of stations increases.

The purpose of the present invention is to solve the above-mentioned problems, and to provide a division method for simultaneous reception from multipoints that can minimize the increase in the number of storage circuits even if the number of stations increases by making the storage circuits common. An object of the present invention is to provide a multi-packet signal recovery device.

[Means for solving problems]

The division multiplexed packet signal restoration device of the present invention adds division information of a certain length to the divided packet signal obtained by dividing the packet signal at each radio station to generate a divided packet transmission signal corresponding to the slot length, and divides the divided packet transmission signal into a time division multiplexed packet signal. A receiving device that receives multiplexed signals includes a storage circuit that stores received divided packet signals as a unit, a detector that detects received divided information, and the divided information detected by this detector as tail information of the divided packet signal. If not, specify the write start address to store this divided packet signal, and if the above division information is the end information of the divided packet signal, after storing this divided packet signal, write the division from the station that sent this divided packet signal. A start address management device that outputs all the write start addresses used for packet signals as read start addresses and immediately reuses these read start addresses as write start addresses again, and a start address management device that receives the write start addresses from the start address management device and A first counter that generates an address signal from the first address to the address of the divided packet signal length, and a first counter that receives the read first address from the first address management device and generates an address signal from this first address to the address of the divided packet signal length. and a second counter.

[Effect]

Fig. 1 is a basic block diagram of the present invention, and Fig. 2 is a basic block diagram of the present invention.
FIG. 2 is a layout diagram of the memory circuit 1 shown in the figure.

The present invention will be described in detail below with reference to FIGS. 1 and 2. In FIG. 1, time-division multiplexed packet signals are input from a terminal 1001. This signal is taken into the memory circuit 1 and the detector 2. The detector 1 detects which portion of the packet signal is the divided packet signal inserted into each TDMA slot, and outputs this detection information to the head address management device M3. Based on this information, the head address management device 3 provides the first counter 4 with a head address for writing this signal into the storage circuit 1 for the divided packet signal. The first counter 4 calculates the amount of data in the slot from the specified starting address to the memory circuit 1.
In order to write to the address, consecutive address signals are sent out sequentially starting from the first address. The memory circuit 1 is allocated as blocks, such as areas 10 to 17 in FIG. Output up to the last address of the area. Further, one area corresponds to one slot capacity, and by the same operation, each divided packet signal sent from each station is written in any area without duplication. If this is the last part of a divided packet sent from a certain station, the detector 2 notifies the head address management device 3 of this fact. Then, when the signals sent from that station are combined, it should become the original packet signal, and the starting address management device 3 stores all the starting addresses corresponding to the divided packet signals that have been stored for that station in the order in which they were stored. It is sent to the second counter 5. 20th
The counter 5 sends the address signal of the area having the designated starting address to the storage circuit 1 in the order of input. The memory circuit 1 sequentially outputs data included in each address from a terminal 1002. Furthermore, the head address management device 3 uses the read head address again to store a new divided packet signal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a block diagram of the head address management device shown in FIG. The configuration of FIG. 3 is the same as that of FIG. 1 except that it is composed of the second counter 5 in FIG. 1 or a buffer 6 which serves as a counter device 50 and can store all the leading addresses of the counter 5. Note that the same reference numerals in FIG. 3, FIG. 4, and FIG. 1 indicate the same components. Therefore, the operation in FIG. 3 is the same as that in FIG. 1 except that the buffer operation in the counter device 50 is added to the operation in FIG.

Therefore, the starting address management device shown in FIG. 4 will be explained below. FIG. 4 shows a selection signal 3003 and a write pulse 3002 in which information obtained in the detector 2 is inputted via a terminal 2001, and the inputted information is decoded to indicate from which station the divided packet signal is sent. Alternatively, the selector 31 outputs the read pulse 3004 and the FI which stores the starting addresses of all areas of the memory circuit 1 in the initial state.
A start address storage circuit 32 constituted by an FO (first in first out) memory, and start address storage circuits 33 and 34 for each station that store the start address of the area where divided packet signals are stored in the storage circuit 1 for each partner station.
and a station-by-station counter 35 that counts and accumulates the number of start addresses stored in the station-by-station start address storage circuits 33 and 34, respectively.
and 36.

Next, to explain the operation when writing a divided packet signal to the storage circuit 1, as a result of decoding by the selector 31, the selector 31
If writing, outputs a write pulse 3002,
At the same time as one starting address is output from the starting address storage circuit 32, this address is input to the starting address storage circuit 33 or 34 for each station selected by the selection signal 3003, and is further sent to the first counter 4 from the terminal 2003. It will be done. The first counter 4 uses the write pulse outputted from the terminal 2002 as a load and start pulse to generate an address for one slot length of data. Also, write pulse 300
2 is counted by a selected station-specific counter 35 or 36 in order to memorize the number of reads, and always counts the number of leading addresses used for a certain station. Although only two of each of the station-specific start address memory circuit and the station-specific counter are shown in FIG. 4, the number of each is equal to the number of stations, and the station-specific start address memory circuit is F I I" O It's memory.

Next, to explain reading, if the result decoded by the selector 31 is the last divided packet signal,
The sequence of signals stored for that station up to that point is 1
Since it consists of two packet signals, it can be output. Therefore, the selector 31 outputs a read signal 3004.

When the station-specific counter selected by the selection signal 3003 receives the signal 3004, it outputs the start addresses stored in the same number of station-specific start address storage circuits as the current count number to the terminal 20.
04 to the buffer 6.

Next, the second counter 5 continuously reads data from the area of the storage circuit corresponding to the sent head address, and the packet signal is reproduced. Further, the start address outputted from the start address storage circuit for each station is input again to the start address storage circuit 32 through 3006 and is reused. Since the first address is set in a loop as described above, there will be no conflict due to double use.

〔Effect of the invention〕

As explained above, according to the present invention, the memory capacity h of the Congo Song Dynasty
t is multiplied by the number of stations in equation (1)! g - whereas maximum packet length x number of stations + amount to be stored while outputting maximum packet length --------------------
−−−−−−−−−−−−−−−−−−−−−−−−(
2> is sufficient. In other words, if the number of C1 stations is n, the amount to be stored while outputting the maximum packet length is expressed as (1) Equation X n - (2) Equation -Cxn2-C=C(n''
-1)...(3) As the number of stations increases, the present invention has the effect that the storage capacity of the present invention is smaller than that of the conventional restoring device.

[Brief explanation of the drawing]

FIG. 1 is a basic block diagram of the present invention, FIG. 2 is a layout diagram of the memory circuit of FIG. 1, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is the starting address of FIG. 3. FIG. 5, which is a block diagram of the management device, is a block diagram of a typical conventional division multiplexed packet signal restoration device. DESCRIPTION OF SYMBOLS 1... Memory circuit, 2... Detector, 3... Starting address management device, 4... First counter, 5... Second counter, 6... Passer, 31...・Selector, 32・
... Starting address storage circuit, 33.34... Starting address storage circuit for each station, 35.36... Counter for each station. 40% trust

Claims (1)

[Claims] A fixed length of division information is added to the divided packet signal obtained by dividing the packet signal at each wireless station to generate a divided packet transmission signal corresponding to the slot length, and a receiving device that receives a signal obtained by time-division multiplexing the divided packet transmission signal receives the divided packet signal. a storage circuit that stores divided packet signals as a unit; a detector that detects the received divided packet information; and a write header that stores this packet signal when the divided information detected by this detector is not the end information of the divided packet signal. Specify the address,
When the above division information is the end information of the divided packet signal, after storing this divided packet signal, all the write start addresses used for the divided packet signal from the station that sent out this division information are read out and output as the start address. , a start address management device that immediately reuses this read start address as a write start address again, and a first address management device that receives the write start address from the start address management device and generates an address signal from this start address to an address of the divided packet signal length. 1 counter and a second counter that receives a read start address from a start address management device and generates an address signal from this start address to an address of the divided packet signal length. Device.