JP3116872B2 - Interface converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface conversion apparatus for accommodating signal lines having different formats, and more particularly, for accommodating signal lines having a plurality of formats efficiently and easily changing the accommodation structure. Related to a simple interface converter.

[0002]

2. Description of the Related Art With the diversification of communication applications, the need for accommodating a line having a format different from that of a conventional analog subscriber line has increased with the diversification of communication applications. In this situation, there has been invented an interface converter having a function of absorbing a difference in the format configuration of a line to be accommodated. is there.

FIG. 11 shows the configuration of such a conventional interface converter. This interface converter includes a demultiplexer 1102 in which a signal line from an external subscriber exchange (not shown) is input / output, and converters 1103 ₁ ,..., 1103 _n for basic interfaces. Conversion circuit 11 for subscriber
04 _1, ..., it is composed from 1104 _n. Basic interface for converting circuits 1103 _1, ..., the 1103 _n, respectively basic interface circuits 1105 _1, ...,
1105 _n are connected and the subscriber conversion circuit 110
4 ₁ ,..., 1104 _n have subscriber circuits 110 respectively.
6 _1, ..., 1106 _n is connected.

[0004] Basic interface circuit 1105₁,…,
1105_nCommunication data from is connected to each
Basic interface circuit 1103₁, ..., 1103
_nAfter being converted to a common format by the
A subscriber switching center (not shown) multiplexed by 102
Sent to Subscriber circuit 1106₁, ..., 1106 _n
Communication data from the subscribers connected to each
Conversion circuit 1104₁, ..., 1104_nWith common forma
After being converted to a packet,
And sent to the subscriber exchange (not shown)
become. It is also sent from a subscriber exchange (not shown).
The multiplexed signal is handled by the demultiplexer 1102.
Distributed to conversion circuits with an interface.
Individual format in the interface conversion circuit
Is converted.

[0005] In previous subscriber exchanges, since the format configuration of the basic interface circuit and the format configuration of the subscriber circuit represented in one frame of the line were different, it was impossible to multiplex and communicate as it was. However, in this interface converter, in order to match the 8-bit format configuration of the subscriber circuit,
The format of the basic interface circuit including the 8-bit audio signal and the 1-bit control signal is rearranged. By reconfiguring the format configuration in this way, it is possible to easily multiplex a line having a plurality of different format configurations with one multiplexer.

FIG. 12 shows the contents of such a format reconfiguration. In one frame 1220 composed of lines L1 to Ln having a fixed length of 32 bits,
The line L1 contains the subscriber line transmission data 1201 and the line L4 contains the basic interface line transmission data 1210.
Has been restructured as a new format. The subscriber line audio data 1201 is composed of 8-bit audio data 1202 and 8 out of 32-bit transmission data.
It is composed of invalid bits 1203, 1204, and 1205. The basic interface line transmission data 1210 includes, among the 32-bit transmission data, 8-bit valid communication data 1211 and 1212 and a 1-bit control signal 1213 corresponding to the valid communication data 1211.
1-bit control signal 1214 corresponding to valid communication data 1212, 6-bit invalid bit 1215, and 8
It consists of invalid bits 1216 of the bits. By setting an invalid bit at an extra bit position in one line in this way, the same as that of the subscriber line voice data 1201 and the basic interface line transmission data 1210 is used.
Since it can be recognized as 1-bit data having a 2-bit length, multiplexing can be easily performed.

[0007]

However, such a conventional interface converter requires a conversion circuit corresponding to the format configuration of each line to be accommodated.
Therefore, since a conversion circuit capable of accommodating a plurality of lines is usually used, if a conversion circuit having a specific format configuration is used, other subscriber lines cannot be efficiently accommodated. Further, when a subscriber line having a new format configuration is accommodated, it is necessary to change the control circuit and the like of the conventional conversion circuit, so that there is also a problem in maintainability. Further, since it is necessary to output a control signal corresponding to the subscriber's circuit, there is a problem that the scale of the firmware of the control circuit becomes large, and the design period for creation and evaluation becomes long.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interface conversion device which can efficiently accommodate a plurality of lines having different format configurations and can easily change the line to be accommodated even if the line changes.

[0009]

According to the first aspect of the present invention, (a) a subscriber that accommodates a line signal as transmission information and outputs a subscriber identification signal indicating the type of format of the accommodated line signal. Line accommodation means, (b)
A multiplexing / distributing means for receiving a line multiplexed signal in which the transmission information and the subscriber circuit control information are multiplexed, and for demultiplexing the line multiplexed signal between the subscriber line accommodating means and an upper station as an exchange; (C) identification means for identifying the type of the format of the line accommodated by the subscriber line accommodating means based on the subscriber identification signal output by the subscriber line accommodating means; and (d) a plurality of different formats. A control information storage means for storing control signal information for converting the configuration; and (e) the control information storage means corresponding to the identification result by the identification means and the subscriber circuit control information separated by the multiplex distribution means. Control information output means for outputting control signal information; and (f) input / output to / from the multiplex distribution means based on the control signal information output from the control information output means. To and a format converting unit for converting a format configuration of the line signals input and output to the subscriber line accommodation unit and the format structure of the line signal to the interface conversion device.

That is, in the first aspect of the present invention, the type of the interface of the subscriber circuit connected by the identification means can be identified. further,
Based on the identification result and the subscriber circuit control information separated by the multiplexing / distributing means, control signal information for performing conversion of different format configurations, which is stored in the control information storage means, can be obtained. As a result, a common control signal can be used for the subscriber circuits having different interfaces, so that the lines of the subscriber circuits having different interfaces can be efficiently accommodated with simple firmware. Further, even if a change occurs in the configuration of the accommodation line, it can be easily handled.

According to the second aspect of the present invention, (a) a subscriber line accommodating means for accommodating a line signal as transmission information and outputting a subscriber identification signal indicating a type of a format of the accommodated line signal; B) Multiplexing distribution for receiving a line multiplexed signal in which transmission information and subscriber circuit control information are multiplexed, and for demultiplexing the line multiplexed signal between the subscriber line accommodating means and an upper station as an exchange. Means for identifying the type of line format accommodated by the subscriber line accommodating means based on the subscriber identification signal output by the subscriber line accommodating means;
An individual control means for outputting an individual control signal based on the identification result by the identification means and the subscriber circuit control information separated by the multiplex distribution means; and (e) outputting a timing control signal corresponding to the identification result of the identification means. And (f) an individual control signal and a format configuration of a line signal input / output to / from the multiplexing / distribution unit and a format configuration of a line signal input / output to / from the subscriber line accommodating unit based on the timing control signal. And a format conversion means for performing the conversion.

That is, according to the second aspect of the present invention, it is possible to identify the type of the interface of the subscriber circuit connected by the identification means. further,
Format conversion is performed by an individual control signal and a timing control signal based on the identification result and the subscriber circuit control information separated by the multiplexing / distributing means.
As a result, a common control signal can be used for the subscriber circuits having different interfaces, so that the lines of the subscriber circuits having different interfaces can be efficiently accommodated on a small scale.

According to a third aspect of the present invention, in the interface converter according to the second aspect, the individual control means stores the individual control signal information corresponding to the identification result of the identification means and the subscriber circuit control information. It has storage means, and outputs individual control signals from the individual control signal storage means based on the identification result and the subscriber circuit control information.

That is, according to the third aspect of the present invention, the individual control signal is output from the individual control signal storage means. Thus, if the storage contents of the individual control signal storage means are changed, the lines of the subscriber circuit having different interfaces can be efficiently accommodated with simple firmware, and even if the configuration of the accommodated lines changes, it can be easily handled. Will be able to do it.

According to a fourth aspect of the present invention, in the interface converter according to the second aspect, the timing control means stores timing control signal information corresponding to the identification result of the identification means; The control signal storage means outputs a timing control signal based on the identification result.

That is, in the invention according to claim 4, the timing control signal is output from the timing control signal storage means. Thus, if the storage contents of the timing control signal storage means are changed, the lines of the subscriber circuit having different interfaces can be efficiently accommodated with simple firmware, and even if the configuration of the accommodated lines changes, it can be easily handled. Will be able to do it.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an interface according to an embodiment of the present invention.
2 shows a configuration of a base conversion device. Below,
Interface converter is 2.048Mbps
Interface and four types of subscribers accommodating four lines
Control signals from a higher-level station that is an exchange
Suppose there is. This interface converter uses line control
Unit 101 and a plurality of interface conversion circuits 102₁,
102_Two, ..., 102 _nAnd These inns
Interface conversion circuit 102₁, 102_Two, ..., 102_n
Subscribers with different format configurations
Circuit 103₁, 103_Two, ..., 103_nIs connected
You. Interface conversion circuit 102_Two, ..., 102_nof
The configuration is the interface conversion circuit 102₁It's basic
These conversion circuits are not shown in the drawings.
You. Therefore, about this interface converter
Is the interface conversion circuit 102₁Focus on the explanation
Do.

The line control unit 101 includes an upper multiplex distribution circuit 10 for inputting and outputting multiplex signals from an external higher station (not shown).
4 and a control circuit 105 and a lower multiplex distribution circuit 106 connected to the upper multiplex distribution circuit 104. The control circuit 105 transmits the control signal multiplexed to the multiplex signal input from the upper station to the upper multiplex distribution circuit 104.
Is separated and input. When a line signal is input from the upper multiplex distribution circuit 104, the lower multiplex distribution circuit 106 converts the multiplexed line signal into the corresponding subscriber circuits 103 ₁ , 103 ₂ ,.
3 _n . At this time, the interface conversion circuit converts the data into an individual format corresponding to each subscriber circuit.
The lower multiple distribution circuit 106, the interface converter 102 _1, 102 _2, ..., the transmission signals 1 to 102 _n
17 _1, 117 _2, ..., when 117 _n is output to the upper multi-distribution circuit 104, has these transmission signals so as to output the multiplexed. These transmission signals 117 _1, 117 _2, ..., 117 _n includes an interface conversion circuit 102 _1, 102 _2, ..., the 102 _n, are converted from a separate format interface for each subscriber circuit to the common format. This common format is a format configuration when transmitted from the line control unit 101 to an upper station.

The interface conversion circuit 102 _1, subscriber circuit 103 and the interface identification circuit 107 to the subscriber identification signal 111 ₁ from ₁ is connected, the identification result signal 1 output from the interface identification circuit 107
12, a control signal conversion circuit 108 that outputs an individual control signal 114 based on a control signal 113 output from the control circuit 105, and a timing control signal 115 based on an identification result signal 112 output from the interface identification circuit 107. a timing signal generation circuit 109, composed of a format conversion circuit 110 to change the format structure of a signal between the lower multiple distribution circuit 106 and the subscriber circuit 103 ₁ on the basis of the individual control signal 114 and the timing control signal 115 Have been.

[0022] The interface conversion device is adapted to allow more subscriber identity signal 111 ₁ output from the subscriber circuit 103 _1, identifying the type of interface of the subscriber circuit. Based on an identification result signal 112 which is a result of identifying the interface type of the subscriber circuit, control signals 114 and 115 output from a control signal conversion circuit 114 and a timing signal generation circuit 115
And it is capable to change the signal format configuration between the subscriber circuit 103 ₁ and the line control unit 101.

FIG. 2 shows a main part of the configuration of the subscriber circuit shown in FIG. Since this subscriber circuit accommodates four lines as described above, the subscriber multiplexing circuit 201
Are connected to subscriber interface circuits 202, 203, 204, and 205 corresponding to four subscriber terminals 206. A transmission signal from the subscriber terminal 206 is multiplexed by the subscriber multiplexing circuit 201 and output to the corresponding interface conversion circuit 102. Also, the corresponding interface conversion circuit 102
The multiplexed signal 116 inputted from is input to the subscriber multiplexing circuit 201 after being separated and input to any of the subscriber interface circuits 202, 203, 204, and 205 as destinations.

The subscriber circuit 103 ₁ outputs a subscriber identification signal 111 ₁ for specifying the type of interface of the subscriber circuit. In this interface converter, since there are eight types of subscriber circuits, the interface converter is constituted by a 3-bit signal. By setting this subscriber circuit to “000” for type A and “001” for type B, the interface identification circuit of the interface conversion circuit 102 ₁ connects the connected subscriber circuit 103 _1.
Interface type can be identified.

FIG. 3 specifically shows a signal for outputting such a subscriber identification signal to the interface identification circuit. As described above, the subscriber circuit 103 ₁ is provided with the subscriber identification output unit 301, and the interface conversion is performed by associating the logical level “H” with “1” and the logical level “L” with “0”. When connecting the subscriber circuits having different interface circuits 102 _1, and is capable of recognizing by decoding the subscriber identification signal at interface identification circuit 107. For example, since the subscriber identification output unit 302 outputs “001” as a subscriber identification signal, it can be identified as a type B subscriber circuit.

As described above, the interface identification circuit 107
A subscriber identification signal 111 ₁ from the subscriber circuit 103 ₁
Thus, the result of identifying the type of the connected interface is output as the identification result signal 112. The identification result signal 112 is input to the control signal conversion circuit 108 and the timing signal generation circuit 109. The individual control signal 114 and the timing control signal 115 output from the control signal conversion circuit 108 and the timing signal generation circuit 109 allow the line signal of the common format configuration on the line control unit 101 side and the subscriber circuit 103
The format configuration between the line signals of the individual format configuration on _one side is converted. In such an individual format configuration, there is an individual format for the audio signal and the control signal separated by the upper multiplex distribution circuit 104.

[0027] Figure 4 illustrates a construction of a common format of the line signals 117 ₁ shown in FIG. In this common format structure, 1 frames F ₁ and "line 1 data" 401, and "line 2 data" 402, "line 3
It comprises data "403" and "line 4 data" 404. In such a format configuration, transmission and reception of a line signal from the line control unit 101 to an upper station are performed.

[0028] FIG. 5 is a diagram showing an arrangement of individual format of the line signals 116 ₁ of the audio signal shown in FIG. The individual format configuration of the audio signal differs for each subscriber circuit. The audio signal separate format configuration of FIG. 5 (a), 1 frames F ₁ is "" Line 1 Data "," unused area "," Line 2 Data "," unused area "," line 3 data "," Unused area "," line 4
"Data,""unusedarea" 501, and multiplexes four lines. In the audio signal individual format configuration shown in FIG.
₁ is configured as “line 1 data”, “line 2 data”, “line 3 data”, “line 4 data” 510 to multiplex four lines. FIG. 5 (c)
In the audio signal individual format configuration, one frame F ₁
Are "line 4 data", "line 3 data", "line 2
"Data", "line 1 data" 520, and multiplexes four lines.

FIG. 6 is a diagram showing an arrangement of individual format of the line signals 116 ₁ of the control signal shown in FIG. In the control signal individual format configuration of FIG.
“Control signal 1” 601 in frame 1 (F ₁ ) and “control signal 2” 6 in frame 2 (F ₂ ) of the eight multiframes
02,..., “Control signal 8” 603 in frame 3 (F ₈ ).
A control signal is transmitted as shown in FIG. FIG.
The control signal separate format configuration of (b), the frame 1 (F ₁₎ to the "control signal 1" of 8 multiframes 6
11, the frame 2 (F ₂₎ "control signal 2" 612, frame 3 (F ₃₎ to the "control signal 3" 613, ... are adapted to deliver a control signal as. In the control signal individual format configuration of FIG. 6C, “control signal 1” 621 in frame 1 (F ₁ ), “control signal 1” 622 in frame 2 (F ₂ ), and frame 3
A control signal is sent to (F ₃ ) like “Control signal 1” 623,. There is a subscriber circuit having the above-described eight types of interfaces by combining an audio signal having an individual format configuration as shown in FIG. 5 and a control signal having an individual format configuration as shown in FIG.

Returning to FIG. 1, the description will be continued. As a result of identifying the type of interface by the subscriber identification signal 111 ₁ , the individual control signal 1 corresponding to this interface is determined.
14 and a timing control signal 115 are generated. The individual control signal 114 is divided into the identification result signal 112 by the control signal conversion circuit 108 and the control signal 11 output from the control circuit 105.
3 is generated. The control signal conversion circuit 108 includes an identification result signal 112 and a control signal 113
Output the individual control signal 114 from the memory.

FIG. 7 shows such a control signal conversion circuit 10.
8 shows an outline of the memory configuration of FIG. This control signal conversion circuit has a total of 10 bits including an upper address 3 bits 701 indicating an interface type of the subscriber circuit, a middle address 4 bits 702 indicating 16 types of control signals from the upper station, and a lower address 3 bits 703. , An 8-bit length data 704 is output.

That is, as shown in FIG. 6A, the control signal 5 of the 16 types of control signals from the higher-level station is controlled by the type A subscriber circuit of FIG. When performing, the upper address 3 bits 70
1 indicates “000” indicating type A and the middle address 702
Represents “0101” indicating the control signal 5, and “control signal 1 of the subscriber circuit A type”, “control signal 2 of the subscriber circuit A type”,
.., "Subscriber circuit A type control signal 8" is stored. Thus, the corresponding control signal is periodically repeated when reading the lower address 3 bits 703, so that the control signals 1 to 8 are output from the data terminal as a control signal of 8 bits in total. As shown in FIG. 6B, when the control signal 5 is controlled for the type B subscriber circuit of FIG. 3 which alternately transmits control signals in even and odd frames, the upper 3 bits indicate the type B. "001" and the middle address is the control signal 5
"0101" indicating that
The "control signal 1 of the subscriber circuit type B" and the "control signal 2 of the subscriber circuit type B" are stored in bit 1 of the data 720. The data 721 is not used as an unused area. 6 (c), in the case of the subscriber circuit type C which transmits the same control signal every frame, the upper 3 bits 701 indicate "010" indicating the type C, and the middle address 4 bits 702 indicate the control. A control signal corresponding to bit 0 of the data terminal corresponding to "0001" indicating signal 1 may be stored.

The timing control signal 115 is generated by the timing signal generation circuit 109 from the identification result signal 112 based on the subscriber identification result 111 ₁ . The timing signal generation circuit 109 has a memory configuration such that the timing control signal 115 is output from the identification result signal 112 similarly to the control signal conversion circuit 108.

FIG. 8 shows an outline of a memory configuration of such a timing signal generation circuit 109. This timing signal generation circuit includes an upper address 3-bit 801 indicating the type of interface of the subscriber circuit;
The timing control signal 115 is output from 8 bits 802 for one frame of the interface of 048 Mbps. The output data 803 is one frame 25
Only the bits of the timing control signal necessary for six bits are stored.

Using the individual control signal 114 and the timing control signal 115 as described above, the conversion between the individual format configuration and the common format configuration is performed by the format conversion circuit 110.

FIG. 9 shows a main part of the configuration of such a format conversion circuit 110. This format conversion circuit includes a memory 901 and a selector 902 for selecting a read value from the memory. The input data 903 to the memory 901 is supplied with the individual control signal 114 from the control signal conversion circuit 108. The control signal 904 of the memory 901 and the selector control signal 906 of the selector 902 are
09 is input. As described above, by using the timing control signal 104 as a read / write signal to the memory 901 and a selector control signal, the individual format configuration and the common format configuration are converted, and the individual control signal 115 is converted to the line signal having the individual format configuration. 116 ₁ is multiplexed.

FIG. 10 shows a timing chart when the individual control signal 115 is multiplexed by the format conversion circuit 110 using the timing control signal 104. FIGS. 10A-1 to 10-3 are timing charts of the 3-bit timing control signal 104. FIG. FIGS. 10 (b-1) to (b-8)
5 is a timing chart showing a data line 905 read from a memory 901. FIG. 10C shows a multiplexed signal 907 output from the selector 902. Assuming that 8-bit data is input to the individual control signal 903, FIG.
In period T ₁ of 0, the timing control signal 104 is "00
Therefore, only the data line (b-1) corresponding to the bit 0 of the individual control signal 903 is output because it is 0 ". The selector 902 is an 8-input selector, and outputs the data line according to" 000 "of the selector control signal 906. (B-1)
Is selected as the multiplexed signal 907 by the data line (b-
1) is output. In period T ₂ of FIG. 10, a timing control signal 104 is because it is "001", and outputs only the data line corresponds to bit 1 of the individual control signals 903 (b-2). The selector 902 has a selector control signal 90 as an 8-input selector.
In order to select the data line (b-2) by "001" of No. 6, the data line (b-2) is output as the multiplexed signal 907. As described above, the 8-bit data of the individual control signal 903 can be multiplexed into the multiplex signal 907 during the period from T _{1 to} T ₈ . By changing the storage contents of the timing control signal of the timing generation circuit 109 in this way, it is possible to cope with multiplexing of different formats.

[0038]

As described above, according to the first aspect of the present invention, the control signal for format conversion corresponding to the result of identifying the interface of the subscriber circuit is output. The subscriber circuit can be efficiently accommodated, and it is possible to easily cope with a change in the accommodation configuration.

According to the second aspect of the present invention, the individual control signal and the timing control signal are generated based on the result of identifying the interface of the subscriber circuit. On the other hand, since a common control signal can be used, it is possible to accommodate a line of a subscriber having a small and different interface and to change the accommodation configuration.

Further, according to the third aspect of the present invention, since the individual control signal information has a memory configuration, efficient accommodation of a line of a subscriber circuit having a different interface and a change in the accommodation configuration can be performed with a simple firmware. It can be realized.

According to the fourth aspect of the present invention, since the timing control signal information has a memory configuration, efficient accommodation of a subscriber circuit having a different interface and a change in the accommodation configuration can be realized with simple firmware. Will be able to do it.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of a configuration of an interface conversion device according to an embodiment of the present invention.

FIG. 2 is a block diagram specifically showing a main part of a configuration of a subscriber circuit 103 shown in FIG. 1 of the embodiment.

FIG. 3 shows a subscriber identification signal 11 shown in FIG. 1 of the present embodiment.
1 shows the generation circuit of FIG.

FIG. 4 is an explanatory diagram showing a common format configuration of a line signal 117 according to the present embodiment.

FIG. 5 is an explanatory diagram showing an individual format configuration of an audio signal of a line signal 116 according to the present embodiment.

FIG. 6 is an explanatory diagram showing an individual format configuration of a control signal of a line signal 116 according to the present embodiment.

FIG. 7 is a control signal conversion circuit 1 of the embodiment shown in FIG.
FIG. 8 is an explanatory diagram showing an outline of a memory configuration 08.

FIG. 8 is an explanatory diagram showing an outline of a memory configuration of the timing signal generation circuit 109 shown in FIG. 1 of the present embodiment.

FIG. 9 is a block diagram illustrating an outline of a configuration of the format conversion circuit 110 illustrated in FIG. 1 according to the present embodiment.

FIG. 10 is a timing chart for explaining multiplexing of individual control signals according to the present embodiment.

FIG. 11 is a block diagram illustrating a main part of a configuration of a conventional interface conversion device.

FIG. 12 is an explanatory diagram showing a state of reconfiguration of a line signal format in a conventional interface conversion device.

[Explanation of symbols]

101 line control unit _{102 1, 102 2, ...,} 102 n interface converter _{103 1, 103 2, ...,} 103 n subscriber circuit 104 higher multiplex distribution circuit 105 control circuit 106 backward multiplexing distribution circuit 107 interface identification circuit 108 control signal conversion circuit 109 a timing signal generating circuit 110 format conversion circuit _{111 1, 111 2, ...,} 111 n subscriber circuit identification signal 112 identification result signal 113 control signal 114 individual control signal 115 timing signals _{116 1, 116 2, ...,} 116 n Subscriber circuit specific format signal 117 ₁ , 117 ₂ ,..., 117 _n Common format signal 201 Multiplex circuit 202, 203, 204, 205 Subscriber interface circuit 206 Subscriber terminal 301 Subscriber circuit type A 302 Subscriber circuit type B

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/02 H04L 12/50 H04Q 1/30-1/56 H04Q 3/42 H04Q 3/52-3 / 62 H04Q 3/70-3/74 H04Q 11/00-11/04

Claims (4)

(57) [Claims] 1. A subscriber line accommodating means for accommodating a line signal as transmission information and outputting a subscriber identification signal indicating a type of a format of the accommodated line signal, wherein said transmission information and subscriber circuit control information are Multiplexing / distributing means for receiving the multiplexed line multiplexed signal, and for demultiplexing the line multiplexed signal between the subscriber line accommodating means and an upper station as an exchange; Identification means for identifying the type of the format of the line accommodated by the subscriber line accommodation means based on the obtained subscriber identification signal, and control information storage for storing control signal information for converting a plurality of mutually different format configurations From the control information storage means, the identification result by the identification means and the subscriber circuit control information separated by the multiplex distribution means. Control information output means for outputting control signal information corresponding to the control signal information; and, based on the control signal information output from the control information output means, a format configuration of a line signal input / output to / from the multiplexing / distribution means and the subscriber line. An interface conversion device, comprising: a format conversion unit that converts a format configuration of a line signal input / output to / from a storage unit. 2. A subscriber line accommodating means for accommodating a line signal as transmission information and outputting a subscriber identification signal indicating a type of a format of the accommodated line signal, wherein said transmission information and subscriber circuit control information are Multiplexing / distributing means for receiving the multiplexed line multiplexed signal, and for demultiplexing the line multiplexed signal between the subscriber line accommodating means and an upper station as an exchange; Identification means for identifying the type of the format of the line accommodated by the subscriber line accommodating means based on the obtained subscriber identification signal; and an identification result by the identification means and the subscriber circuit control information separated by the multiplex distribution means. Individual control means for outputting an individual control signal based on a timing of outputting a timing control signal corresponding to the identification result of the identification means Conversion means for converting the format configuration of the line signal input / output to / from the multiplexing / distribution unit and the format configuration of the line signal input / output to / from the subscriber line accommodating unit based on the individual control signal and the timing control signal. An interface conversion device, comprising: a format conversion unit for performing a conversion. 3. The individual control means has an individual control signal storage means for storing an identification result of the identification means and individual control signal information corresponding to the subscriber circuit control information. 3. The interface conversion device according to claim 2, wherein an individual control signal is output based on the identification result and the subscriber circuit control information. 4. The timing control means includes timing control signal storage means for storing timing control signal information corresponding to the identification result of the identification means, and based on the identification result from the timing control signal storage means. 3. The interface conversion device according to claim 2, wherein the interface conversion device outputs a timing control signal.