JPH11285036A - Time switch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time switch circuit capable of being employed to a device even when an accommodating capacity is increased and applicable to an inexpensive cross connect transmitter. SOLUTION: Input data 241 -243 received by signal processing sections 201 -203 are subject to time division multiplex processing on a common bus 21 in a transmission timing controlled by a multiplex control section 22 and a desired time slot is demultiplexed in a reception timing controlled by the multiplex control section 22. Then a time switch function is realized by replacing an optional time slot with a data memory of a signal processing section 204 receiving a multiplex signal on the common bus 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time switch circuit in a cross-connect transmission device, and more particularly, to a time switch circuit in a cross-connect transmission device in which the number of constituent units is minimized.

[0002]

2. Description of the Related Art In recent years, various forms of communication, such as facsimile and image, have been performed with the progress of computerization. Against the background of such diversified information communication modes, digital switching using a digital transmission technology capable of flexibly adapting to an unspecified number of media has become the mainstream of the switching technology. One of the functions required for this switching technology is a switching function for switching connections of terminals and communication lines. In order to realize this switching function, it is composed of a time switch circuit for exchanging time slots on a multiplexed line called a time-divided highway, and a space switch circuit for mutually switching the incoming and outgoing highways for each time slot. ing.

A time switch circuit has a function equivalent to a matrix circuit, and can be constituted by an integrated memory device. In a digital exchange realizing a switching function, such a time switch circuit is configured by arranging two to three stages according to the scale of the exchange. On the other hand, a space switch circuit is used to connect time switch circuits to each other for the purpose of expanding a circuit network. Considering the integration of the time switch circuit and the role of the time switch and the space switch, in order to accommodate a large-capacity line with digital switching and realize the switching function at low cost,
It is considered more effective to increase the capacity of the time switch circuit than to the space switch circuit.

FIG. 4 shows an outline of the configuration of a conventionally proposed time switch circuit. The time switch circuit 10 includes a plurality of Irigata paths 11 _1, 11 _2, ..., a multiplexing circuit 12 for multiplexing the input signals from the 11 _N, multiplex circuits 1
2 and a control memory 1 for generating a write timing of each time slot of the highway multiplexed by the multiplexing circuit 12 to the data memory 13.
4 and a separation circuit 16 for separating the output signal from the highway read from the data memory 13 into output routes 15 ₁ , 15 ₂ ,..., 15 _N.

In the control memory 14, a data memory designation entry for designating a storage location of the data memory 13 is stored in advance corresponding to each time slot of the highway multiplexed by the multiplexing circuit 12. Therefore, writing to the data memory 13 is performed for each time slot of the highway based on the data memory designation entry of the control memory 14. Once the data of each time slot of the incoming highway is once stored in the data memory 13 based on the data memory designation entry of the control memory 14, the data is sequentially read out by using a counter circuit, so that it is again multiplexed as a multiplexed signal. Will be sent to Here, the data memory 1 by the control memory 14
By changing the data memory designation entry to No. 3, the multiplexed line output from the data memory 13 with respect to the highway multiplexed by the multiplexing circuit 12 can generate a multiplexed signal in which time slots are exchanged. it can.

FIG. 5 shows a time switch circuit in which the number of incoming routes and the number of outgoing routes are three in order to explain the operation principle of the time switch circuit shown in FIG.
In this switch circuit Dekataro 1 Irigata passage 11 ₁
To 5 _2, the Irigata passage 11 ₂ to the Dekataro 15 _1, it is assumed that communicate respectively connecting Irigata path 11 ₃ to Dekataro 15 _3. Therefore, the control memory 14 has a channel 1 of the incoming highway as a data memory designation entry to the data memory 13 corresponding to each time slot of the incoming highway 17.
“# 2” means connecting the time slot of the incoming highway to channel 2 of the outgoing highway, “# 1” means connecting the time slot of the channel 2 of the incoming highway to the channel 1 of the outgoing highway, "# 3" indicating that the time slot of the highway channel 3 is connected to the outgoing highway channel 3 is stored in advance. Therefore, each time slot of the incoming highway 17
Based on the information stored in the control memory 14, the data is stored in the data memory 13 in the order of channel 2, channel 1, and channel 3 of the incoming highway.

The data memory 13 has a predetermined counter circuit (not shown), and can sequentially read information stored in the data memory 13 at a predetermined read timing. Therefore, in each time slot of the outgoing highway 18, the multiplexed signal from which the channel 2, channel 1, and channel 3 of the incoming highway have been read is transmitted to the separation circuit 16. Separation circuit 16 exits into output path 15 ₁ to channel 1 of the highway, output to the output path 15 ₃ the channel 3 of the highway exit to the output path 15 ₂ to channel 2 of the highway are separated respectively Therefore, each time slot of the outgoing highway is separated and output to each outgoing route. In this way, by exchanging the time slots of the multiplexed highway, communication with an arbitrary partner can be performed.

In the above-described time switch circuit, data is written to the data memory 13 so that the time slots are exchanged by the control memory 14. However, the data of each time slot of the incoming highway is sequentially written to the data memory 13. When writing and reading, time slots can be exchanged by reading according to the reading order stored in the control memory 14.

In addition, a space switch circuit has conventionally been used for asynchronous signals, but a time switch circuit has also been proposed which also performs switching of the asynchronous signals. A technique relating to such a switching circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-87832, “Cross-Connect System for Digital Transmission”.

[0010]

Such a conventional time switch circuit can be easily constituted by a memory element, and is therefore often integrated. However, when it is necessary to accommodate more than the capacity that can be accommodated on the integrated circuit, a plurality of time switch integrated circuits are combined,
The required capacity was ensured by determining whether to use it in combination with the space switch circuit. However, as the capacity to be accommodated increases, the scale of the memory circuit as described above increases, and the scale of the hardware for cross-connect is increasing. Has been invited.

It is an object of the present invention to provide a time switch circuit which can be easily introduced into a device even when the capacity to be accommodated is large and which is used in a low-cost cross-connect transmission device.

[0012]

According to the first aspect of the present invention, (a) a common bus as a transmission path for multiplexed signals;
(B) transmission timing generating means for generating a transmission timing of a multiplexed signal transmitted on the common bus to a predetermined time slot; and (c) entering the common bus with the transmission timing generated by the transmission timing generating means. (D) receiving timing generating means for generating, as a receiving timing, a time corresponding to a time slot of the input signal transmitted at the transmitting timing generated by the transmitting timing generating means; E)
Receiving means for receiving the multiplexed signal on the common bus at the reception timing generated by the reception timing generating means; and (f) exchanging the time slot of the multiplexed signal received by the receiving means to change the output signal on the output path. The time switch circuit is provided with a time slot replacing means to be generated.

That is, according to the first aspect of the present invention, the transmission timing generation means generates the transmission timing of the multiplexed signal to the predetermined time slot on the common bus as the transmission path of the multiplexed signal, and the reception timing generation means. Then, the time corresponding to the time slot of the input signal transmitted at the transmission timing generated by the transmission timing generating means is generated as the reception timing. The transmitting means transmits the input signal of the incoming route on the common bus at the transmission timing generated by the transmission timing generating means, and the receiving means multiplexes the signal on the common bus with the receiving timing generated by the receiving timing generating means. A predetermined time slot of a signal is received. The time slot received in this way is
A time switch circuit is configured by exchanging time slots by time slot exchanging means.

According to the second aspect of the present invention, (a) a plurality of common buses as transmission lines for multiplexed signals, and (b) multiplexing for selecting one of these common buses and transmitting on the selected common bus. Transmission timing generation means for generating transmission timing of a signal to a predetermined time slot;
Transmitting means for transmitting an input signal of an incoming route to the common bus selected by the transmission timing generated by the transmission timing generating means; and (d) a common bus selected by the transmission timing generated by the transmission timing generating means. Receiving time generating means for generating a time corresponding to a time slot of an input signal to be transmitted as a receiving timing, and (e) transmitting a multiplexed signal on a common bus selected by the receiving timing generated by the receiving timing generating means. The time switch circuit is provided with: receiving means for receiving; and (f) time slot exchanging means for exchanging time slots of the multiplexed signal received by the receiving means to generate an output signal on an outgoing route.

That is, according to the second aspect of the present invention, the transmission timing generating means determines the transmission timing of the multiplexed signal to a predetermined time slot for one selected from the plurality of common buses as the transmission path of the multiplexed signal. At the same time, the reception timing generation unit generates a time corresponding to a time slot of an input signal transmitted at the transmission timing generated by the transmission timing generation unit as the reception timing. The transmission signal generated by the transmission timing generation means is used to transmit the input signal of the incoming route onto the selected one common bus, and the selected common bus is transmitted at the reception timing generated by the reception timing generation means. A predetermined time slot of a multiplex signal on the bus is received. The time slots received as described above are configured to be time switching circuits by exchanging the time slots by the time slot exchanging means.

According to the third aspect of the present invention, (a) a common bus as a transmission path for multiplexed signals, and (b) transmission means for transmitting an input signal of an incoming path to the common bus at a predetermined transmission timing, A receiving means for receiving a multiplexed signal on the common bus at a predetermined reception timing; and a time slot exchanging means for exchanging time slots of the multiplexed signal received by the receiving means to generate an output signal on an outgoing route. A plurality of signal processing units, and (c) selecting one of these signal processing units as an input route and transmitting an input signal of the selected input route to a predetermined time slot of a multiplexed signal on a common bus. Timing and a reception timing as a time corresponding to a time slot transmitted on the common bus at the transmission timing by selecting another signal processing unit as an outgoing route. Thereby and a resulting reception timing generation unit to the time switch circuit.

That is, according to the third aspect of the present invention, there is provided a common bus as a transmission path for multiplexed signals, and a plurality of signal processing units for connecting communication between an incoming route and an outgoing route via the common bus.
A transmission / reception timing generator for generating a transmission timing for transmitting a multiplexed signal to each time slot to the common bus and a reception timing for receiving a desired time slot from the multiplexed signal on the common bus. Thus, a time switch circuit is configured.
Each signal processing unit transmits an input signal of an incoming path to the common bus at the transmission timing generated by the transmission / reception timing generation unit when transmitting a signal to the common bus, and transmits / receives the transmission timing when receiving a signal from the common bus. Multiplexed signals from the common bus are received at the reception timing generated by the generation unit, and time slots are exchanged to generate output signals on the outgoing route. The transmission / reception timing generator,
A transmission timing for selecting one of the plurality of signal processing units and transmitting an input signal on an incoming route to a predetermined time slot of a multiplexed signal on a common bus, and selecting another signal processing unit as an outgoing route The time corresponding to the time slot transmitted on the common bus at the transmission timing is generated as the reception timing, and each is notified to the selected signal processing unit.

According to the fourth aspect of the present invention, (a) a plurality of common buses as transmission lines for multiplexed signals and (b) one of the common buses selected from these common buses by a predetermined transmission timing signal are input to the common bus. Transmitting means for transmitting an input signal of a route;
Receiving means for receiving a multiplexed signal on one of a plurality of common buses selected from a plurality of common buses with a predetermined reception timing signal, and exchanging time slots of the multiplexed signal received by the receiving means to output an output path A plurality of signal processing units comprising a time slot replacement means for generating a signal,
(C) One of the signal processing units is selected as an input path, and one of the plurality of common buses is selected, and a signal is input to a predetermined time slot of a multiplex signal on the selected common bus. A transmission timing signal for transmitting the input signal of the path, and a signal processing unit and a common bus to which the input signal of the input path is transmitted by the transmission unit among the plurality of common buses as the output path. And a transmission / reception timing generator for respectively generating a reception timing as a time corresponding to a time slot transmitted on the common bus by a transmission timing signal.

That is, according to the present invention, a plurality of common buses as transmission paths for multiplexed signals, one of the plurality of common buses is selected, and an incoming path and an outgoing path are selected via the common bus. A plurality of signal processing units for connecting the communication of the channels, and a transmission timing for transmitting these signal processing units to each time slot of the multiplexed signal with respect to the common bus selected as the transmission line and the common signal selected as the transmission line. A time switch circuit is constituted by a transmission / reception timing generator for generating a reception timing for receiving a desired time slot from a multiplex signal on the bus. Each signal processing unit transmits an input signal of an incoming route to the selected common bus at a transmission timing generated by the transmission / reception timing generation unit when transmitting a signal to the selected common bus, and When receiving a signal from the common bus, the multiplexed signal from the common bus is received at the reception timing generated by the transmission / reception timing generation unit, and the time slot is exchanged to generate an output signal on the output path. The transmission / reception timing generator selects one from a plurality of common buses,
Further, one of the plurality of signal processing units is selected to transmit the input signal of the incoming route to a predetermined time slot of the multiplexed signal on the common bus, and another signal processing unit is selected as the outgoing route. Then, a time corresponding to the time slot transmitted on the common bus selected as the transmission path at the transmission timing is generated as the reception timing, and each is notified to the selected signal processing unit.

According to a fifth aspect of the present invention, in the time switch circuit according to the third or fourth aspect, each of the signal processing unit and the timing generation unit is integrated.

In other words, according to the fifth aspect of the present invention, since the signal processing unit and the timing generation unit are each integrated into an integrated circuit to be a minimum unit of the device, the signal processing unit and the timing generation unit can be easily adjusted according to the capacity of the cross-connect transmission device. Appropriate accommodation capacity can be secured.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

First Embodiment

FIG. 1 shows the outline of the configuration of the time switch circuit in the first embodiment of the present invention. The time switch circuit, a plurality of signal processing unit 20 _1, 2
0 _2, 20 _3, 20 _4, these signal processing units 20 ₁ to 20 ₄
Common bus 21 as a transmission path for multiplexed signals transmitted and received between
If, from the common signal processing unit 20 ₁ to 20 ₄ each bus 21
And a multiplexing control unit 22 for instructing generation of timing for transmission or reception from the common bus 21. As a signal processing unit 20 ₁ to 20 ₄ are respectively the same configuration, the following shall be described only the signal processing unit 20 _1, will not be described signal processing unit 20 ₂ to 20 _4.

The signal processing unit 20 ₁ includes an external interface unit 23 ₁ for interfacing the main signal to an external device (not shown), a common bus 21 to the input data 24 ₁ which is the main signal of the input signal input from the external device a timing generation unit 25 ₁ and a reception timing to retrieve the data of a predetermined time slot of the multiplex signal on the common bus 21 and the transmission timing for transmitting to a predetermined time slot of the multiplexed signal can be generated respectively above, the timing generator Part 2
5 The common bus 21 at the transmission timing generated by ₁
And a data transmission unit 26 ₁ for transmitting input data to a predetermined time slot of the multiplex signal above. Further, a data receiving unit 27 ₁ for receiving data of a predetermined time slot of a multiplexed signal on the common bus 21 at a reception timing generated by the timing generating unit 25 ₁ , and a time for receiving data extracted by the data receiving unit 27 ₁ . and a data memory 28 ₁ which switch the slot.

The timing generation unit 25 ₁ of the signal processing unit 20 _1, and is capable of generating a predetermined transmission timing and reception timing by control signals generated by the multiplexing control unit 22. That multiplexing controller 22 sends the relative timing generator 25 _to 253 ₄ of the respective signal processing units 20 ₁ to 20 _4, to a particular time slot of the multiplex signal on the common bus 21 to each of the signal processing unit performs And control the reception. For example multiplexing controller 22, a predetermined time multiplexed signals on the common bus 21 to the input data 24 ₁ which is the main signal of the input signal that is input via the external interface unit 23 ₁ from the external device in the signal processing unit 20 ₁ While transmitting to the slot,
0 Another signal processing signal processing unit of the multiplex signal on the common bus 21 by the reception timing corresponding to the time slots transmitted by the signal processing unit 20 ₁ with respect to section 20, such as _4
The time slot data transmitted by ₁ can be received.

The multiplexing control unit 22 transmits the signal processing unit 2 on the transmitting side to each time slot of the multiplexed signal on the common bus 21.
0 ₁ 20 ₄ of and generating the transmission timing to each timing generator 25 _to 253 ₄ to assign each multiplex signal on the common bus 21 is a signal processing unit 20 21 _to
0 Each input data 24 _{1-24 4 4} will be transmitted in a time division. Receiving side is by so as to generate the reception timing of the time corresponding to the desired time slot on the common bus 21 to either one or a plurality of signal processing units 20 ₁ to 20 _4, transmitted from the transmission side The received time slot can be captured on the receiving side. The multiplexed signal transmitted in a time-division manner as described above is fetched on the receiving side, and then an arbitrary time slot is replaced by each data memory.

In the following, the signal processing units 20 ₁ , 20 ₂ , 20 ₃
Multiplexed in a time-division manner from the signal input from the
The operating principle is described as outputting _0-4.

FIG. 2 is a timing chart schematically illustrating the operation principle of time division multiplexing of the time switch circuit shown in FIG. FIG.
(C), the signal processing unit 20 ₁ to 20 each timing generator 25 21 _to to multiplex in time division input data from ₃
5 is ₃ that represents the transmission timing 301 _{to 303} generated by. Such transmission timing 30 ₁
30 _3, are generated by being controlled by the multiplexing control unit 22. FIG. 2D shows multiplexing of transmission signals 31 _{1 to} 31 _{3 in} which input data 24 _{1 to} 24 ₃ are transmitted in predetermined time slots on the common bus 21 at such transmission timings 30 ₁ to 30 ₃ , respectively. It is a signal. Thus on the common bus 21 is inputted to the signal processing unit 20 ₁ to 20 ₃ Input Data 24
_{1-24 3} is transmitted as a signal multiplexed form in the transmission signal 31 _{1-31 3} time division transmitted respectively.

The multiplexing controller 22 while generating a multiplexed signal multiplexed in time division, the timing generator 25 ₄ to generate a reception timing 32 to the signal processing unit 20 ₄ for receiving the multiplexed signal To instruct. Thus, the timing generator 25 _4, the reception timing between the signal processing unit 20 ₁ corresponds to the time slot that is transmitted 32
It generated as, to receive the multiplexed signal on the common bus 21 to the data receiving unit 27 _4. FIG. 2 (e) shows a reception timing 32 for retrieving the input data of the signal processing unit 20 ₁ from the multiplexed signal shown in Figure 2 (d). Such reception timing 32, the received multiplex signal 3 of the data receiving unit of the signal processing unit 20 ₄ as shown in FIG. 2 (f)
3, by receiving the transmission signal 31 ₁ from the signal processing unit 20 ₁ can perform communication with the signal processing unit 20 ₁ and the signal processing unit 20 _4. Thus, for example, FIG.
By generating a reception timing 32, as shown in (g), the signal processing unit 20 ₄ of the data receiving unit 27 ₄ as shown in FIG. 2 (h), multiple multiplexed by time division on the common bus 21 The signal can be received as a reception multiplex signal 32.

The reception multiplex signal 32 is stored in the data memory 28 ₄
, Each time slot is exchanged. As shown in FIG. 4 or FIG. 5, the exchange of the time slots is performed by controlling the write entry to the data memory according to the information stored in the control memory and reading the data in a predetermined order at the time of reading. Do. In this way, the main signal inputted to the signal processing unit 20 ₁ to 20 ₃ are multiplexed, the form of the data time slot has been replaced is output via the external interface 23 ₄ as output data 29 _4.

As described above, the time switch circuit according to the first embodiment converts the input data input to each signal processing unit on the common bus 21 in a time division manner at the transmission timing controlled by the multiplex control unit 22. The multiplexing is performed, and a desired time slot is separated at the reception timing controlled by the multiplexing control unit 22. The signal processing unit that has received the multiplexed signal on the common bus 21 implements a time switch function by exchanging arbitrary time slots using the data memory.

The conventional time switch circuit shown in FIG. 4 requires a data memory capacity corresponding to "(input highway) .times. (Multiplicity of multiplexed signal)". The capacity of each data memory of the signal processing unit only needs to be equivalent to “(multiplicity of multiplexed signal)”. That is,
Although the memory capacity required for exchanging time slots is the same for the entire time switch circuit, the first embodiment requires only a small capacity for each data memory. That is, since it is generally desired that a memory element be incorporated in a limited device, a large-capacity memory is more expensive in terms of demand. It shows that it is advantageous. Further, in the related art, a new time switch circuit is also provided to change the accommodation capacity, and a complicated change operation such as a change of a large-capacity control memory is required, and the expandability is poor. However, in the time switch circuit according to the first embodiment, the signal processing unit is a low-cost minimum constituent unit, so that it is possible to easily cope with an increase in capacity and to change only the timing of the multiplex control unit. Extensible.

Second Embodiment

FIG. 3 shows an outline of the configuration of a time switch circuit according to a second embodiment of the present invention. The time switch circuit includes a plurality of signal processing units 40 ₁ , 4
0 _2, ..., 40 _M, a plurality of common bus 4 as a transmission path of the multiplex signal transmitted and received between the signal processing unit 40 ₁ to 40 _M
1 ₁ to 41 _N and, multiplexing for generating a timing for receiving from one of the transmission or the common bus 41 ₁ to 41 _N from each signal processing unit 40 ₁ to 40 _M to one of the common bus 41 ₁ to 41 _N And a control unit 42. As a signal processing unit 40 ₁ to 40 _M are each identical configuration, hereinafter, it is assumed that only describes the signal processing unit 40 _1, the description thereof is omitted for the signal processing unit 40 ₂ to 40 _M. The same parts as those of the time switch circuit in the first embodiment shown in FIG.

The signal processing unit 40 ₁ includes an external interface unit 23 ₁ for interfacing the main signal to an external device (not shown), a common bus 41 to the input data 24 ₁ which is the main signal of the input signal input from the external device one of _1-41 any one selected by multiplexing signals of a predetermined transmission timing Similarly common bus 41 _{1-41 N} or generate for transmission to a time slot on the the selected common bus of the _N select one timing generator 43 ₁ for generating a reception timing to retrieve data from a predetermined time slot of the multiplex signal on the the selected common bus is selected at the transmission timing generated by the timing generator 43 ₁ and a data transmission unit 26 ₁ for transmitting input data to a predetermined time slot of the multiplex signal on the common bus has. Further, the data receiving unit 2 that captures data of a predetermined time slot of a multiplexed signal on the common bus selected at the reception timing generated by the timing generating unit 43 ₁ .
7 _1, data memory 28 ₁ interchanging the time slots of the received data extracted by the data receiving unit 27 ₁
And a selector 44 for switching a common bus transmitted from the data transmitter 26 ₁ or received by the data receiver 27 ₁ to a common bus selectively controlled by the timing generator 43 ₁ .
Have _one .

The timing generation section 43 ₁ of the signal processing unit 40 ₁ is not only the generation of a predetermined transmission timing and reception timing by control signals generated by the multiplexing control unit 42, a common destination or receiver Bus selection control can be performed. Accordingly, the multiplexing control unit 42 sets each of the signal processing units 40 ₁ to 40 _M
Can each signal processing unit with respect to the timing generation unit 43 ₁ ~ 43 _M controls the transmission and reception to a particular time slot of one of multiple signals on the common bus of the common bus 41.

The operating principle of the time switch circuit in the second embodiment is the same as that of the time switch circuit in the first embodiment except for the control of selecting the common bus 41 during transmission and the control of selecting the common bus 41 during reception. Since the operation principle is the same, the description is omitted.

As described above, the time switch circuit in the second embodiment selects any one of a plurality of common buses and inputs the selected common bus to each signal processing unit. At the transmission timing controlled by the multiplex control unit 42, the input data is multiplexed in a time division manner. At the reception timing controlled by the multiplex control unit 42, a desired time slot is selected from the multiplexed signal on the selected common bus. Separated. The signal processing unit that has received the multiplexed signal realizes a time switch function by exchanging arbitrary time slots by using a data memory.

The time switch circuit according to the second embodiment can select a common bus as a transmission line in addition to the effect of the time switch circuit according to the first embodiment. By increasing the number of common buses in this way, it is possible to greatly increase the capacity of the time switch circuit in the first embodiment.

Although the time switch circuit in the first embodiment has been described as having four signal processing units, it is not limited to the number of signal processing units.

In the time switch circuits of the first and second embodiments, the transmission timing or the reception timing is generated by each timing generation section in accordance with an instruction from the multiplex control section. , The transmission / reception timing may be directly generated. That is, if the transmission / reception timing to the common bus in the plurality of signal processing units can be controlled, the effect of the present invention can be obtained.

[0044]

As described above, according to the first aspect of the present invention, the input signal of the incoming route is multiplexed on the common bus according to the transmission timing and the reception timing to the common bus, and the output signal of the output route is output. Are separated, and the time slots of the multiplex signal taken in from the common bus are exchanged. As a result, even when the data storage capacity is large, a time switch portion equipped with a large-capacity memory is not required, and inefficient expansion by using a plurality of time switch circuits and a complicated control memory change accompanying the expansion are required. The use of a space switch, which is difficult to work and miniaturize, can be eliminated, and a time switch circuit that is inexpensive and can easily accommodate an increase in storage capacity can be configured.

According to the second aspect of the present invention, the transmission timing and the reception timing to the common bus determine
Select one of multiple common buses, multiplex the input signal of the incoming route on the selected common bus, separate the output signal of the outgoing route, and take the time of the multiplexed signal taken from the selected common bus. Slots are exchanged. Thus, in addition to the effect of the first aspect, by increasing the number of common buses, the capacity can be efficiently increased.

According to the third aspect of the present invention, in addition to the effect of the first aspect, the transmission / reception timing generation unit controls transmission / reception of transmission signals between a plurality of signal processing units collectively. Therefore, it is possible to flexibly respond to the increase or decrease of the capacity to be accommodated.

According to the fourth aspect of the invention, in addition to the effect of the second aspect, the transmission / reception timing generation unit controls transmission and reception of transmission signals between a plurality of signal processing units collectively. Therefore, it is possible to flexibly respond to the increase or decrease of the capacity to be accommodated.

According to the fifth aspect of the present invention, the signal processing unit and the transmission / reception timing generation unit are each integrated into an integrated circuit, so that they are packaged as the minimum configuration unit, thereby reducing the capacity to be accommodated in the device. Efficient,
In addition, an inexpensive time switch circuit can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a configuration of a time switch circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram schematically showing a timing chart for explaining the operation principle of time division multiplexing of the time switch circuit in the first embodiment.

FIG. 3 is a block diagram illustrating an outline of a configuration of a time switch circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an outline of a configuration of a conventionally proposed time switch circuit.

FIG. 5 is an explanatory diagram for explaining the operation principle of a conventionally proposed time switch circuit.

[Explanation of symbols]

20 _{1 to} 20 ₄ Signal processing unit 21 Common bus 22 Multiplex control unit 23 ₁ to 23 ₄ External interface unit 24 _{1 to} 24 ₄ Input data 25 _{1 to} 25 ₄ Timing generation unit 26 _{1 to} 26 ₄ Data transmission unit 27 _{1 to} 27 ₄ Data receiving unit 28 _{1 to} 28 ₄ Data memory 29 _{1 to} 29 ₄ Output data 30 ₁ to 30 ₃ Transmission timing 31 _{1 to} 31 ₃ Transmission signal 32 Reception timing 33 Reception multiplex signal

Claims (5)

[Claims] 1. A common bus as a transmission path for a multiplexed signal, transmission timing generation means for generating a transmission timing of a multiplexed signal transmitted on the common bus to a predetermined time slot, and a transmission timing generation means for generating the transmission timing Transmitting means for transmitting an input signal of an incoming route to the common bus at the transmitted transmission timing; and receiving timing corresponding to a time slot of the input signal transmitted at the transmission timing generated by the transmission timing generating means. Receiving timing generating means for generating the multiplexed signal, receiving means for receiving the multiplexed signal on the common bus at the receiving timing generated by the receiving timing generating means, and exchanging time slots of the multiplexed signal received by the receiving means. Time slot exchange means for generating an output signal of an outgoing route. Time switch circuit, characterized by. 2. A plurality of common buses as transmission lines for a multiplexed signal, and one of the common buses is selected, and transmission timing of a multiplexed signal transmitted on the selected common bus to a predetermined time slot is generated. Transmission timing generating means, transmitting means for transmitting an input signal of an incoming route to the selected common bus at the transmission timing generated by the transmission timing generating means, and transmission timing generated by the transmission timing generating means Receiving timing generation means for generating, as reception timing, a time corresponding to a time slot of the input signal transmitted to the selected common bus, and the common timing selected by the reception timing generated by the reception timing generating means. Receiving means for receiving the multiplexed signal on the bus, and receiving by the receiving means Time switch circuit characterized by comprising a time slot replacement means for generating an output signal of the output path by interchanging the time slots of the multiplexed signal. 3. A common bus as a transmission path for a multiplexed signal, transmission means for transmitting an input signal of an incoming path to the common bus at a predetermined transmission timing, and a multiplexed signal on the common bus at a predetermined reception timing. A plurality of signal processing units comprising: receiving means for receiving; and a time slot replacing means for replacing the time slots of the multiplexed signal received by the receiving means to generate an output signal on an outgoing route. One of which is selected as an incoming route, the transmission timing for transmitting an input signal of the selected incoming route to a predetermined time slot of a multiplexed signal on the common bus, and another signal as an outgoing route. A transmission / reception timing for selecting a processing unit and generating a reception timing as a time corresponding to a time slot transmitted on the common bus at the transmission timing. Time switch circuit, characterized by comprising a generation unit. 4. A plurality of common buses as transmission lines for multiplexed signals, transmission means for transmitting an input signal of an incoming route to one of the common buses selected by a predetermined transmission timing signal, Receiving means for receiving a multiplexed signal on one of the plurality of common buses selected from the plurality of common buses with a predetermined reception timing signal, and exchanging time slots of the multiplexed signal received by the receiving means to determine an output path A plurality of signal processing units each including a time slot replacement unit for generating an output signal; selecting one of these signal processing units as an input path and further selecting one of the plurality of common buses; The transmission timing signal for transmitting an input signal on an incoming route to a predetermined time slot of a multiplexed signal on a selected common bus; another signal processing unit as an outgoing route; A common bus to which an input signal of an incoming path is transmitted by the transmitting unit is selected from the common bus, and a reception timing as a time corresponding to a time slot transmitted on the common bus by the transmission timing signal is selected. A time switch circuit comprising: a transmission / reception timing generation unit that generates each of them. 5. The time switch circuit according to claim 3, wherein each of the signal processing unit and the timing generation unit is integrated.