JP2002204284A - Circuit for generating aos test signal conforming to ccsds - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CCSDS(Consultative Committee for Space Data System) conforming AOS(Advanced Orbiting Systems) test signal generation circuit capable of simulatively generating data for a CCSDS conforming AOS service while guaranteeing the continuity of frames. SOLUTION: This generation circuit has a VCID(VCD ID) storing part (11), a VCDU(Virtual Channel Data Unit) counter part (12) an APID(Applied Process ID) storing part (13), a sequence counter part (14) and a data buffer where test data are written independently and guarantees the continuity of counters. A data buffer is made to be a double buffer configuration and guarantees the continuity of the frames even when data are changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to CCSDS (CoSDS).
nsultive Committee for
AOS (A) based on Space Data System
advancedOrbiting Systems) Data generation for services, especially CCSDS compliant AOS
The present invention relates to a test signal generation circuit.

[0002]

2. Description of the Related Art A test signal generating circuit is used to simulate data transmitted from a spacecraft to a ground station. AO that simulated data is specified by CCSDS
In the case of the S format, conventionally, all of the pseudo-generated data is once written in a memory, and thereafter, the data is read and output.

FIG. 4 shows an output data format of a test signal generation circuit. The test signal generation circuit sets the format of FIG. 4 as one frame, and repeatedly generates and outputs this frame. Data to be written to memory
All are generated by software and written to single-buffered memory.

When it is necessary to change the contents of data, the output is stopped once and reset by software.
One frame length is a maximum of 1279 bytes.

[0005] VCDU (Virt) included in the frame
The VCDU header consisting of 6 octets is present in the ual Channel Data Unit. This VC
The DU header includes a version number, a VCDU ID [satellite ID, VCID],
VCDU counter, Signaling Field
[Replay flag, spare].

[0006] The VCID is an identifier for putting a plurality of virtual channel data (Virtual Channel Data) on one physical line. The VCDU counter is incremented and added for each transmission frame, and the receiving side monitors the continuity of the frame based on the value.

[0007] The VCDU counter is a counter managed independently for each VCID. FIG. 5 shows details of the VCDU data area shown in FIG. The VCDU data area stores the BPDU (Bit Stream) shown in FIG.
m Data Unit), VCA (Virtual
Channel Access) or an MPDU (Multiplexing Protocol) shown in FIG.
ol Data Unit) is stored.

[0008] When an MPDU is stored in the VCDU data area, the MPDU includes an MPDU header and an MPDU data area, and the MPDU data area includes one or a plurality of CCSDS packets. The CCSDS packet is composed of a packet header of 6 octets and a variable data area according to the data amount.

The packet header includes a version number, a type, a secondary header flag, and an application process ID (APID) for packet identification, a sequence flag and a sequence counter for packet sequence control,
It is composed of a packet length. APID is
Like the above-mentioned VCID, it is an identifier for identifying data according to the application.

[0010] The multiplexing service as described above is a service for obtaining one or more packets from users of different applications and multiplexing them. The sequence counter is a count value that is incremented for each transmission packet, and is used to monitor the continuity of a packet.

FIG. 6 shows a conventional CCSDS-compliant A.
This is a method for implementing an OS test signal generation circuit. The generated data is generated on software in the format shown in FIG. The content of the generated data varies depending on the service required by the spacecraft, and may be assembled from the above-described packet-level data, assembled from the frame-level data, or mixed. The data buffer unit 1 storing the data generated in this way is read out based on the read address given from the read address generation unit 2, and is output as pseudo test data.

Data generated by software generates a plurality of frames according to the capacity of the memory. The generated data is written from the software to the memory. After writing all the data to be generated, the contents of the memory are read out by hardware, parallel / serial converted, and output. When changing the content of data to be generated, the memory readout by hardware must be stopped once, and rewrite must be performed by software.

In the above-mentioned prior art, all the data which is simulated is written in the memory. Therefore, all data for the required number of frames must be written to the memory. Therefore, when matching with the VCDU counter, a memory of 2 ＾ 24 (2 to the 24th power) frame is required per VCID. However, in reality, since the memory is about several megabytes to several hundred megabytes, there is a disadvantage that continuity of frames is not guaranteed. Further, in order to change the content of the generated data, it is necessary to temporarily stop the operation of the hardware, and there is a disadvantage that the writing process requires time.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to pseudo-generate CCSDS-compliant AOS service data while guaranteeing frame continuity. It is an object of the present invention to provide a CCSDS-compliant AOS test signal generation circuit capable of performing the above-mentioned operations.

[0015]

The above object is achieved by generating a frame synchronization pattern, generating a VCID, generating a VCDU counter, generating an APID, and generating a sequence counter. Means,
Means for generating VCDU data or packet data.

Further, the present invention is characterized by including means for switching and outputting each of the generating means, and means for generating a timing for switching.

Further, the means for generating the packet data is characterized in that the generation and the change are performed independently.

Another object of the present invention is to provide a means for generating packet data, wherein the means for generating packet data is provided with overlapping data buffer means, and data writing and reading are alternately used to ensure data continuity. The CC according to any one of claims 1 to 3, wherein
The problem is solved by the SDS-compliant AOS test signal generation circuit.

In the present invention, a part of the data generation realized in the prior art is made independent, and the generation means is switched according to a prescribed format, so that the VCDU counter in the VCDU format and the sequence counter in the CCSDS packet format are continuously output. And output it. Further, the present invention enables a reduction in the write processing time.

[0020]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Referring to FIG. 1, an AOS test signal generation circuit according to the present invention includes a frame synchronization pattern storage unit 3 for storing a frame synchronization pattern, a VCDU header generation unit 4 for generating a VCDU header on a VCDU format, and a CCSDS packet format. It comprises a packet header generator 5 for generating the above CCSDS packet header, a data buffer 6 for generating VCDU data or packet data, a timing memory 7 for controlling data switching timing, and a data switching unit 8. .

The VCDU header generator 4 has two sets of VCIs.
To generate D, two sets of VCID storage units (1, 2) 11 and a VCDU counter unit (1, 2) 1 for counting up for each frame corresponding to the VCID.
And 2.

The packet header generator 5 has four sets of APIs.
In order to generate D, four sets of APID storage units (1 to 4) 13 and a sequence counter unit (1 to 4) that counts up for each packet corresponding to the APID
14.

The combination of the VCID storage unit 11 and the VCDU counter unit 12 and the combination of the APID storage unit 13 and the sequence counter unit 14 can be changed according to the mounting capacity of hardware.

FIG. 2 shows details of the data buffer unit 6 shown in FIG. The data buffer unit 6 includes a double buffer 9 including a buffer unit (A) and a buffer unit (B), and a read address generation unit 10.

FIG. 3 shows details of the data switching section 8 shown in FIG. The data switching unit 8 includes a timing memory address generation unit 15, a timing data reading unit 16, and a data input switching unit 17.

Hereinafter, the operation of the COSDS-compliant AOS test signal generation circuit according to the present invention will be described with reference to FIGS. Before use, the fixed pattern specified by CCSDS is stored in the frame synchronization pattern storage unit 3 by software. In addition, each VCID
The necessary VCID is stored in the storage unit 11 by software before use. Then, each APID storage unit (1
4) 13 stores necessary APIDs by software before use.

The data buffer unit 6 stores the above VCI
The software stores the VCDU data or the packet data generated for each D or APID in the output order. The data buffer unit 6 has a double buffer configuration as shown in FIG. 2, and can perform data writing by software and data reading from hardware separately.

Data is read from one buffer of the double buffer configuration, for example, buffer (A), and data is written to the other buffer (B) during that time. Buffer switching is performed at the end of a frame of output data after the end of writing by software.

The timing memory unit 7 includes the above-mentioned frame synchronization pattern storage unit 3, data buffer unit 6, VCID
The word timing of the output frame to specify the storage unit 11, the APID storage unit 13, the VCDU counter unit 12, and the sequence counter unit 14 is specified. The timing memory unit 7 is specified by software before use.

The data switching section 8 includes a timing memory section 7
Is read out.

The address generator 15 for timing memory shown in FIG. 3 counts sequentially from 0 to [frame length-1], and repeats counting from 0 again. The timing data reading unit 16 reads data at an address corresponding to the count value from the timing memory.

The data input switching section 17 includes a frame synchronization pattern storage section 3, a data buffer section 6, a VCID storage section 11, a VCDU counter section 12,
The data is read out and output while switching the APID storage unit 13 and the sequence counter unit 14. At the time of data reading, the corresponding counter units (VCDU counter unit 12, sequence counter unit 14) are counted up.

The input data can be specified for each word of the timing memory unit 7 by setting the bit assignment in advance as follows. Bit 15: Output data of the frame synchronization pattern storage unit Bit 14: Output data of the data buffer unit Bit 13:-Bit 12:-Bit 11: Output data of the sequence counter unit (4) Bit 10: APID storage unit ( Output data of 4) Bit 9: Output data of sequence counter unit (3) Bit 8: Output data of APID storage unit (3) Bit 7: Output data of sequence counter unit (2) Bit 6: Store APID Output data of unit (2) bit 5: Output data of sequence counter unit (1) bit 4: Output data of APID storage unit (1) bit 3: Output data of VCDU counter unit (2) bit 2: Output data of VCID storage unit (2) bit 1: Output data of VCDU counter unit (1) bit 0 : Output data of VCID storage unit (1) This bit assignment is shown as an example according to the configuration of the counter unit in FIG. Therefore,
If the bit assignment is changed to 16-bit decoding in accordance with the number of counters, it is possible to specify 65536 input data at maximum.

Below, one frame is 1279 bytes, V
A timing memory setting example in the case of two CIDs and no packet data is shown. In this case, the packet header generator 5 is not used. The head word of the frame is word 0. Word 0: 8000h Word 1: 8000h Word 2: 8000h Word 3: 8000h Word 4: 4000h Word 5: 0001h Word 6: 0002h Word 7: 0002h Word 8: 0002h Word 9: 4000h Word 10: 4000h Word 11: 4000h Word 12 Word 4000: Word 1276: 4000h Word 1277: 4000h Word 1278: 4000h Word 1279: 8000h Word 1280: 8000h Word 1281: 8000h Word 1282: 8000h Word 1283: 4000h Word 1284: 0004h Word 1285: 0008h Word 1286: 0008h Word 1287: 0008h Word 1288: 4000h Word 1289: 4000h Word Word 1290: 4000h Word 1291: 4000h Word 2555: 4000h Word 2556: 4000h Word 2557: 4000h With such a setting, data of 2VC (virtual channel) can be output alternately. At this time, each VCDU
The counter counts up alternately in frame units.

Next, a second embodiment of the present invention will be described with reference to the drawings. If the entirety of the timing memory in FIG. 1 is 4000h, all output data will read the contents of the data buffer unit 6, which is the same as that of the prior art. In this case, only the data generated by the software is output.

[0036]

When the present invention is used in the first embodiment,
This has the effect of ensuring continuity between the VCDU counter added to the frame level data and the sequence counter added to the packet level data. In addition, since writing of data by software and reading of data by hardware are performed independently, there is an effect that continuity of data output frames is guaranteed even when data is changed.

In the first embodiment, the number of generated packets and VC
The number of ID / APID occurrences is limited by hardware capacity. On the other hand, when the present invention is used according to the second embodiment, the effect of avoiding the restrictions of the first embodiment can be obtained.

Further, by combining the first embodiment and the second embodiment, it is possible to obtain an effect that many pseudo patterns can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a CCSDS-compliant AOS test signal generation circuit according to the present invention.

FIG. 2 is a block diagram illustrating an example of an internal configuration of a data buffer unit in FIG. 1;

FIG. 3 is a block diagram illustrating an example of an internal configuration of a data switching unit in FIG. 1;

FIG. 4 is a diagram showing an output data format in the CCSDS-compliant AOS format.

FIG. 5 is a diagram showing a part of an output data format of the COSDS-compliant AOS format.

FIG. 6 is a block diagram illustrating a configuration of a CCSDS-compliant AOS test signal generation circuit according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data buffer part 2 Read address generation part 3 Frame synchronous pattern storage part 4 VCDU header generation part 5 Packet header generation part 6 Data buffer part 7 Timing memory part 8 Data switching part 9 Double buffer part 10 Read address generation part 11 VCID Storage unit (1, 2) 12 VCDU counter unit (1, 2) 13 APID storage unit (1-4) 14 Sequence counter unit (1-4) 15 Timing memory address generator 16 Timing data read unit 17 Data input switching Department

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[Procedure amendment]

[Submission date] December 28, 2000 (200.12.
28)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Patent application title: CCSDS-compliant AOS test signal generation circuit

Continued on front page F term (reference) 5K035 AA01 AA03 AA04 BB01 CC10 DD03 FF04 GG03 5K042 AA05 CA02 EA14 FA01 FA15 GA11 LA11 5K047 AA11 AA15 DD03 HH01 KK11 MM24 MM56

Claims (4)

[Claims] 1. A means for generating a frame synchronization pattern, a means for generating a VCID, a means for generating a VCDU counter, a means for generating an APID, a means for generating a sequence counter, and a means for generating VCDU data or packet data. Generating means for generating a COSDS-compliant AOS test signal. 2. A CCSDS-compliant A according to claim 1, further comprising: means for switching and outputting each of said generating means; and means for generating timing for switching.
OS test signal generation circuit. 3. The CCSDS-compliant A according to claim 1, wherein the means for generating the packet data performs the generation and the change independently.
OS test signal generation circuit. 4. The data generating means according to claim 1, wherein said means for generating packet data comprises overlapping data buffer means, and alternately uses data writing and reading to ensure data continuity. 4. The CCSDS-compliant AOS test signal generation circuit according to any one of 1 to 3.