JP2546743B2 - Packet / high-speed packet switch for voice and data - Google Patents

Abstract

A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.

Description

Description: TECHNICAL FIELD The present invention relates to a voice / data packet switch.
s), and more particularly to the architecture of interfaces for packet / high-speed packet networks for such switches.

BACKGROUND OF THE INVENTION Voice and data exchanges are known in the prior art. Packet switches are also known. However, in the past, synchronization has been a problem in controlling voice / data packet switches for controlling devices that send and receive information packets. This problem is related to the problem of dynamically allocating packet bandwidth among the various peripherals attached to the switch for voice and data information. The other relevant element is the architecture of the network interface to the switch. Older switch network interface architectures used the same bus for both data and control. When combined with the problem of dynamically allocating bandwidth to the bus, this network interface architecture results in switches with low switching capacity and throughput. These performance issues become even more important with modern high speed packet protocols. Therefore, it would be desirable to provide a voice / data packet switch with an improved network interface architecture.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a voice / data packet switch with an improved network interface architecture.

Thus, an improved network interface architecture for packet / high speed packet switches is disclosed. This network interface architecture provides both voice and data combination in a single switch using a common packet structure. It allows dynamic allocation of bandwidth based on system loading. This includes not only the bandwidth within the voice or data area of the frame, but also between the voice and data portions. Network interface (N
I) provides a means (NI-bus) to pass all packets through the network interface or to allow packet devices to transfer packets directly between each other. This bandwidth allocation can be easily changed because the control and data memories are synchronized with each other.

The architecture for network interfaces according to the present invention allows control of data packet and bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of data and the allocation of bus bandwidth. The packet device can be controlled at a very high bit rate such as 40 Mbps. It also allows packet devices to forward packets directly. It allows easy reallocation of bandwidth through the use of NI base registers.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a first embodiment of a packet / fast packet switch for voice and data, including an improved network interface.

FIG. 2 shows a network interface bus for the first embodiment.

 FIG. 3 shows a packet.

FIG. 4 is a high level block diagram for the network interface.

FIG. 5 shows a memory map of the network interface.

 FIG. 6 shows an address register.

FIG. 7 shows the data memory area of the processor for the network interface.

FIG. 8 shows a network interface base register.

 FIG. 9 shows the status / control register.

 FIG. 10 shows a virtual circuit register.

FIG. 11 is a timing chart showing the control transfer timing of the network interface.

FIG. 12 is a timing diagram showing data transfer from the device to the network interface when there are no additional bytes.

FIG. 13 is a timing diagram showing a data transfer from the device to the network interface when it has additional bytes.

FIG. 14 is a timing diagram showing data transfer from the network interface to the device.

FIG. 15 is a timing diagram showing data transfer from the device having the largest packet size error or space availability error to the network interface.

FIG. 16 is a timing diagram showing data transfer from a device having a CRC error to a network interface.

FIG. 17 is a timing diagram showing data transfer from a device having an address error to a network interface.

DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1, a network interface 10
It can be seen that 5 is the center of the LAN device (both node and UIM). LAN (both cable and wireless)
The various interfaces in are connected to each other and to the control processor 107 to provide time division and fast packet switching. Information is transferred between these interfaces via a network interface memory 111 which is accessible by the control section of the network interface (both input and output) and by the control processor 107. The flow of information on the LAN side is carried out via a network interface (NI-bus) 101, which sends data, for example 500 per second.
It is designed to pass through up to 10,000 bytes and handle corresponding control information at the same rate. Microprocessor bus 103 couples network interface 105 to control processor 107.

Referring now to FIG. 2, the interaction between network interface memory 111 and NI-bus 101 is shown. The output control circuit, which is part of the network interface chip 109, sequentially passes through the control memory 211 and sends address and command bytes to the control bus 20.
Give to 3. Each device on the control bus 203 has an address. When a device is addressed by the control bus, the byte following the address tells the device whether to drive or listen to the data bus 201. Thus, all NI-bus devices, including network interface 105, listen to control bus 203 and determine whether to listen or drive data bus 201. The output control circuit also sequentially passes through the data memory 213.
If the network interface 105 is driving the data bus 201, the information in the data memory 213 will be output to the data bus 201. If the network interface 105 is listening on the data bus 201, the input control 205 will either accept the data or place it in the appropriate area of the data memory 213. The network interface 105 can simultaneously listen to and drive the bus 101. This allows the network interface 105 to be placed in loopback mode.

FIG. 3 shows the structure of the standard packet 300. When a start packet signal (discussed below) is received from the periphery of NI-Bus 101 (eg, radio links 125, 127, 129), the first byte 301 received by the network interface is a Virtual Circuit ID. This field 301 is used to create control information for up to 256 virtual circuits, that is, a pointer to an area of the NI-memory 111 that holds the destination address of the primary packet. The input circuit uses this information to store the packet information field in the appropriate location in NI-Memory.

The packet length field 303 is then evaluated and checked against the maximum packet size field in the appropriate virtual circuit register, described below. If the packet length is larger than the maximum packet size, the information field of the packet will not be stored.

The address type field 305 is used as an offset into a field of 16 device address registers, each up to 128 bits in length. The appropriate address register, described below, is then compared against the address field 309 in the received packet up to the number of bytes indicated in the address length field 307 of the packet. If the address 309 does not match, the information field 313 is not stored. Note that zero-length addresses are always seen to match, and thus represent all calls.

At the network interface, the CRC checker checks the CRC on all packet headers including the header FCS311. The checker result is zero for a valid header. If the CRC check is not valid, the network interface will generate an end-of-packet signal.

Network interface 105 sets the information field to N
In order to store in the I memory 111, three conditions must be satisfied. The three conditions are as follows.

1. The packet length 303 in the packet header 315 must be less than or equal to the maximum packet size stored in the virtual circuit register.

2. Address 309 in packet header 315 is the address length
Address type 3 for the number of bytes specified by 307
Must be equal to the address contained in the address register specified by 05. In this case, the two addresses need not be essentially the same. This allows group calls.

3. CRC check must be valid.

All of these memory areas are defined in a set of base registers accessible to the control processor 107, described below.

Therefore, the control processor 107 is
And fully define the timing and device selection of the input area. It writes the necessary data to the control area 211 and, if appropriate, the data to the data area 213,
, Which is, for example, the appropriate header to be sent.

The control processor 107 then sets up the appropriate addresses (first read, inter alia, from the personality module containing the electronic serial number of the particular device) and the appropriate virtual circuit parameters (eg, data packet interface to the control processor). , And set the appropriate pointer in the base register.

Referring to FIG. 4, the network interface 10
Five are shown. The network interface is 6
It is composed of individual basic blocks. That is, input 405, output 407, NI-bus decode 409, memory access control 403, processor interface 207, and memory 111. Memory 111 is not currently included in network interface ASIC 109.

Input block 405 evaluates the header of the incoming packet and determines what to do with the packet. When the packet start indication 417 is received with the data clock 419, the input section 405 loads the header 315 and determines if the packet 300 is for this device and determines the routing. Once the routing is determined, the information field of the packet is loaded into the appropriate area of network interface memory 111.

The input block 405 is an 8-bit wide bidirectional data bus,
It is connected to the outside via the network interface data bus 201. NI data bus 201 has a maximum clock rate of 5 MHz. Even in this case, the cycle of the data clock signal 419 is
The data can be stably obtained from the memory for longer than the data access time. The packet start signal 417 is combined with the data clock signal 419 to indicate the first byte of the packet 300. The data bus 201 is the same bus connected to the output block 407. The network interface 105 can only input from or output to a single interface device at any given time. Packet end signal
421 is generated by the network interface when it receives the last byte of the packet indicated by the packet length 303 contained in the packet header 315. This signal 421 is used by the interface device to determine when additional bids, such as signal strength information, should be sent to the network interface 105.

The timing for signals on NI-Bus 101 is shown in FIGS.

The input block 405 can address up to 62 interface devices, but the bus loading limit is 12. The interface devices include wireless, LAN, and telephone interfaces. Time is allocated between each frame via the NI control bus 203 to allow these devices to pass packets to each other.

The output block 407 performs two main functions. First
In addition, it is the NI databus 201 at the appropriate time during the frame.
A packet is output from the network interface 105 to the above interface device. Second, it outputs control information to the NI control bus 203. NI control bus 203 is 5 MHz
Is an 8-bit wide bus at the maximum clock rate of. Since the cycle of the control clock signal 427 is longer than the access time of each device on the control bus 203, stable control data is supplied on the bus, and the data clock 419 is also on the data bus 201.
Since it is longer than the access time of each of the above devices, stable data is supplied on the bus. The output clock 407 passes through the data and control buffers at the clock rate set by the clock visor in the NI base register. The position in the data buffer is synchronized with the position in the frame via the period offset in the NI base register.

NI-bus decode 409 listens to the addresses and commands on NI-bus 101. It is a broadcast
Or decode all commands that have a network interface address. It has an input clock of 40
5 provides control to notify when to listen to data bus 201 and provides output block 407 to control when data bus 2
Notify whether to drive 01. It also output block 40
Decode skip N clock command for 7.

Processor interface block 207 provides an interface between control processor 107 and network interface 105. It also contains the NI base registers described in a later section. The control processor 107 must read from and / or write to the memory and registers at the network interface 105. Processor interface 207 allows control processor 107 to access memory / registers without slowing down the operation of network interface 105.
Depending on the frequency of control processor 107 memory accesses allowed by network interface 105, zero to two wait states are injected via DTACK. DTACK is generated for both reads and writes.

The network interface 105 is the control processor 107
Will occupy 64K bytes of space in the memory map. The NI base register occupies addresses hex FC00 through hex FC17 in this space. Processor interface 207 supports both byte and forward operations on NI registers and memory. NI
Memory 111 is organized in a manner similar to 68000 memory.

The network interface 105 interrupts the control processor 107 via the INT line. The INT line is cleared when the control processor responds with an interrupt acknowledge, ITACK. The NI 105 has two interrupt sources. The first is at the beginning of the frame,
And the second is the reception of packets destined for the control processor 107. These interrupts can be enabled and disabled by software.

The network interface 105 can be reset via a reset line from the processor 107. It must be part of the power up sequence. The net result of NI reset is to ensure that the control bus 203 does not output any commands. The reset must be active low and low for at least one microsecond.

Note that the processor bus signal of the processor interface 207 is a bus signal of the Motorola 68000 processor, and the timing specification thereof is referred to the description given on the latter part of page 31.

The memory access control block 403 inputs 405 access to the appropriate number of network interface memory 111,
It is assigned to the output 407 and the block of the processor interface 207. Each block requires the maximum number of memory accesses in the byte time (200 nanoseconds). Each block has a maximum number of memory accesses assigned to it per byte time.

The memory block 111 is the network interface 105.
Provides all the memory required by. It contains not only memory for packets, but also memory for the registers needed for routing and addressing at the network interface 105.

Referring to FIG. 5, a memory map 500 of memory 111 is shown. The memory 111 is divided into 5 sections. That is, virtual circuit register 501, address register 503, processor data 505, control buffer 509,
And the data buffer 507. The header 315 of the incoming packet 300 contains information that, when used in combination with virtual circuit registers and address registers, routes the packet through the network interface 105. Standard packet 300 is shown in FIG.

The network interface 105 can interrupt the control processor 107 via the INT line. INT
The line is cleared when NI receives an interrupt acknowledge, ITACK. NI can generate two types of interrupts. The first is at the beginning of each frame. The second is a packet that the control processor 107
When received and directed to. Any of these interrupts can be disabled by software via status / control register 900.

Virtual circuit register 501 is used with circuit ID field 301 of incoming packet 300 to determine where in memory 111 the packet should be stored. There are a total of 256 circuit IDs, some of which are reserved for special packets like reset, frame sync and control data. The circuit ID 301 included in the packet is used in combination with the virtual circuit register pointer in the NI base register to determine the address of the virtual circuit register. The contents of the virtual circuit register are used to determine the routing and characteristics of the packet.

The next section of memory is the address register 503. This section contains 128-bit registers. This allows a device to have multiple addresses of multiple types. The arrangement 600 of the address register memory 503 is the sixth
It is shown in the figure. A device can have 16 different addresses of various types, and these addresses can change. 128 bits were selected due to the requirement of each device's unique electronic serial number.

Incoming packet 300 has address type 305, address length 30
Including 7 and address 309. Address type 305 is NI
Used in combination with the address register pointer in the base register to determine the proper address register address in memory. Address length 307 is used to determine how many bytes of the address register are read from memory. The bytes to be read from memory are next in the address field 30 of the packet.
Compared with the content of 9. This determines if the packet is being sent to this device. Cello-long addresses are always seen as consistent and therefore represent all calls.

Referring again to FIG. 5, processor data in memory
Section 505 provides storage for all incoming packets destined for control processor 107. Managing this section of memory is more complex than the other sections. Many packets need to be stored in this area of memory during a single frame. The types of packets stored in this section of memory are frame sync, control, occasional data and LAN data.

A circular buffer is used for the processor data section of memory 505. that is
It is implemented using a pointer in the NI base register. A diagram 700 of a section of processor data 505 in memory is shown in FIG.

The organization of packet storage in the processor data buffer is also shown in FIG. Below is a list of the information stored in the buffer for each packet, and the order in which it is stored.

1. Number of bytes of additional information stored after the packet information field (1 byte) 2. Length of packet information field (2 bytes) 3. Packet information field (0-2048 bytes) 4. Additional information Bytes (0-7 bytes) 5. Time stamp (2 bytes) that indicates the time in the frame that the first byte (circuit ID) of the packet header was received. 4 registers in the NI base register for a circular buffer of processor data. Is specified. A diagram 800 of these registers can be seen in FIG. The processor data start register contains the address of the first byte of the circular buffer. This register is written by the control processor 107 and read by the network interface 105. The processor data end register contains the address of the last byte of the circular buffer. This register is also written by the control processor and read by the network interface.

There are two additional registers for the circular buffer. The first is a processor data read register. This register is used by the control processor to inform the network interface of the address of the first byte of the next packet read by the control processor 107. Control processor 107 writes this register only after it has read the entire packet. In other words, the processor data read register always points to the first byte of the packet. The last register is the processor data write register. This register points to the address used and written by the network interface. It is written by the network interface 105 and read by the control processor 107.

The network interface 105 checks to see if there is room in the buffer to write the packet before it is written. If there is not enough space, the packet will not be stored.

Referring again to FIG. 5, control buffer 509 provides storage for address / command bytes used to control NI data bus 201. The address of the control buffer is determined by the control buffer address register in the NI base register. The buffer is loaded by the control processor 107 with the appropriate address / command bytes. It is accessed at the same rate as the clock for output data on NI Databus 201. The buffer is reset at the same time the data buffer is reset to its start position, the address contained in the control buffer address register. This allows synchronization between control and data buffers.

Still referring to FIG. 5, the last section of memory is the data buffer 507. The buffer contains as many bits as there are frames. For a 1 millisecond frame at 40 Mbps, the data buffer contains 40,000 bits, or 5,000 bytes. The address of the data buffer is determined by the data buffer address register in the NI base register and its size is determined by the data buffer size register.

The packet is input block 405 or control processor 107.
Is written in the data buffer 507. When the path (virtual circuit ID) is established, the control processor writes the packet header 315 in the data buffer 507. The input block 405 only transfers the information field 313 of the incoming packet 300. The control processor 107 writes all packets for control, occasional, and LAN data.

The control processor 107 is a network interface
Responsible for initializing the base register, virtual circuit register, and address register. When the routing changes, it must update the virtual circuit register. It is also responsible for writing the packet header to the data buffer for every outgoing packet.

A set of registers is used to program the network interface 105. They control the addresses of output buffers, address registers, and virtual circuit registers, frame synchronization, output buffer size, output clock speed, and interrupts. The Network Interface Base Register consists of 12 consecutive 16-bit registers located at hexadecimal addresses FC00 through FC17 in NI memory space, but is not included in NI memory. A diagram 800 of the register is shown in FIG.

The status / control register 900 is shown in FIG. The status / control register 900 is used to enable interrupts and also to identify what type of interrupt occurred. The register is read / write and is bits 0-7 of the first NI base register.

Referring now to FIG. 9, it can be seen that bit 6 is used to enable packet receive interrupt 901. If bit 6 is set to 1, an interrupt occurs when the packet is received and the signal CP bit is set in the virtual circuit register. Bit 7 is set to 1 when the entire packet is received and the signal CP bit is set in the recollection circuit register. Bit 7 in the status / control register 900 is cleared after being read by the CP.

Bit 4 is used to enable the start of frame interrupt. If bit 4 is set to 1, an interrupt will occur when the NI 105 reaches the beginning of the frame. Bit 5 is set to 1 to indicate that the interrupt was generated by a start of frame. Bit 5 in status / control register 900 is C
Cleared after being read by P.

Both packet receive and start of frame interrupts will be at the same interrupt level for the control processor. CP
Must read the status / control register 900 to determine which caused the interrupt.

Bit 1 of status / control register 900 is used to reset network interface 105. This is the same as power-up reset. The end result of the NI reset is to ensure that the control bus 203 does not output any address. NI can also be reset via a reset line from control processor 107.

CP is bit 0 in status / control register 900
Write 1 to. This is the control bus 203 for the NI 105
Reset and disable. Control bus 203
Remains disabled until CP 107 writes a zero to bit 0 in status / control register 900.

The Clock Divisor register determines the bit rate of the output of the network interface 105. Bits 0-7 of the second NI base register contain the output clock divisor. The register is for reading / writing. The clock divisor is 00
It can be any value between 000000 and 11111111. Table 1 contains the preferred values for the clock divisor and the corresponding bit rate. Clock Visor Value Bit Rate 00000001 40 Mbps 00000010 20 Mbps 00000100 10 Mbps 00001000 5 Mbps 00010000 2.5 Mbps 00100000 1.25 Mbps Table 1-Typical Clock Divisor Sync Offset Registers are used to synchronize data and control buffers to the system frame. To be done. Bits 0-12 of the third NI base register contain the sync offset and read / write. The frame sync packet contains the position of the packet in the frame. When packet 300 is received, the position in data buffer 507 is stored with the packet. Control processor 107 compares the two values to determine if the data buffer is in sync with the frame. If not, control processor 107 loads the offset value into the sync offset register. This register is used to load the data buffer counter at the end of data buffer 507. After the sync offset register is loaded into the data buffer counter, it is cleared by the network interface.

The data buffer size register sets the size of the data buffer in bytes. Bits 0-12 of the fourth NI base register are data buffer size and read / write
Including writing. The data buffer size, in combination with the clock divisor, determines the length of the frame.
Table 2 shows the preferred output buffer size for acceptable frame size as a function of bit rate.
The data buffer can be any size, and the maximum value is determined by the available NI memory.

The data buffer size is used to determine the end of the frame. The counter used for the sequence with the data buffer is compared to the data buffer size. If the counts are equal, the counter is loaded with the value in the simultaneous offset register, the data buffer address is loaded into the counter used to address the data buffer, and the counter buffer address is loaded into the control buffer. Loaded into the counter used.

The control buffer address register defines the start position of the control buffer in the network interface memory. It is the fifth NI base register and read / write. The control buffer address register is used to change the control buffer.

The data buffer address register defines the start position of the data buffer in the network interface memory. It is the sixth NI base register and is read / write. The data buffer address register is used to change the data buffer. This register is used with the virtual circuit pointer register to change the structure of the frame.

The virtual circuit register pointer assumes the top of the address for the virtual circuit register. It is bits 11-15 of the seventh NI base register and is read / write. It provides bits 11-15 of the address for the area of the virtual circuit register of the memory in the network interface memory. Bits 3-10 are provided by the virtual circuit ID of the incoming packet.

The address register pointer defines the upper part of the address for the address register. It is bits 8-15 of the 8th NI base register and is read / write. It provides bits 8-15 of the address for the address register area of the memory in the network interface memory. Bits 4-7 are provided by the Address Type field, and bits 0-3 are generated based on the value of the Address Length field in the incoming packet header.

The processor data buffer start register defines the start of a section of NI memory used to store data destined for the control processor. It is bits 0-15 of the ninth NI base register and is read / write. The processor data area of NI memory is a circular buffer, and this register defines the beginning of the buffer.

The processor data buffer end register defines the end of a section of NI memory used to store data destined for the controlling processor. It is bits 0-15 of the 10th NI register and is read / write. The processor data area of NI memory is a circular buffer, and this register defines the bottom of the buffer.

The processor data read pointer register defines the address of the next packet in the processor data area of NI memory to be read by the controlling processor. It is bits 0-15 of the 11th NI base register and is read / write. The control processor writes this address only after the packet has been completely read from NI memory. After the entire packet has been read, the CP writes the address of the next packet into the processor data read register. The address contained in the processor data read register always addresses the beginning of the packet in NI memory.

The processor data write pointer register defines the next address in the processor data area of the memory written by the network interface. It is bits 0-15 of the 12th NI base register and is read-only. The network interface updates this register when the packet is written to the processor data area of NI memory. NI checks this register against the processor data read repointer register to prevent information from being overwritten.

The parameters of the virtual circuit are contained in the virtual circuit register in the network interface memory. There are banks of 256 virtual circuit registers located contiguously in the memory addressed by the pointer in the NI base register. The contents of the register are shown in FIG.
The register is used by the circuit ID field of the incoming packet, where in the memory the packet should be stored, the maximum allowed packet length, how many bytes are sent after the end of the packet, It determines whether the packet is destined for the control processor and whether the control processor should be interrupted. 25 in total
There are 6 circuit IDs, some reserved for special packets like reset, frame sync, and control data. The circuit ID included in the packet is an offset with respect to the address of the proper virtual circuit register.

Referring now to FIG. 10, the destination address of virtual circuit register 1000 defines where in network interface memory 111 the information field 313 of packet 300 is stored. It is the first word of virtual circuit register 1000. Destination·
The address is the address in NI memory 111 at the beginning of the storage area for the packet with the given virtual circuit ID.

Maximum packet size field is given virtual circuit
Identifies the largest packet transferred for an ID. It is contained in bits 0-15 of the second word of virtual circuit register 1000. The maximum packet size is used as a safeguard to prevent the packet 300 from overwriting memory. If the packet length 303 is larger than the maximum packet size, the information field 313 of the packet 300
Is not stored, and the network interface generates end-of-packet signal 421. See the timing diagrams in Figures 11-17.

All unused circuits to prevent invalid virtual circuit IDs from overwriting memory
The maximum packet size for the ID should be set to zero by the control processor 107.

The Expected Extra Bytes field defines the number of bytes that follow the end of the Information field 313 of the packet 300. It is contained in bits 0 to 2 of the third word of virtual circuit register 1000.

There can be 0 to 7 bytes following the information field 313. This information is sent immediately after the end of packet 300. The device on the NI bus 101 begins transmitting the byte, if any, after the packet end line 421 transitions from low to high. Packet end 421 remains high until all additional bytes are received or packet start 417 goes low. The device must still generate the data clock signal 419 for each additional byte. See the timing diagrams in Figure 11 through Figure 17.

The signal CP flag is used to determine whether a packet for a given virtual circuit ID should generate a signal to processor 107. This is useful when the packet is written in the processor area of the network interface memory 111. The flag is bit 3 of the third word of virtual circuit register 1000. If this bit is a 1, then bit 7 (901) of the status / control register 900 will be set to a 1 when the packet is being written to the processor area of NI memory 111. If the status / control register 900 bit 6 (903) is 1
If set to
Will be generated in.

The CP data flag indicates whether or not the packet having this circuit ID is directed to the control processor 107. If the flag is 1, the information field 3 of the packet 300
13 will be written to the processor area of NI memory 111 and the address contained in the destination address will be ignored. The flag is bit 4 of the third word of virtual circuit register 1000.

The cipher type field specifies the type of encryption to be used for a given virtual circuit. The field is bits 3 and 6 of the third word of the virtual circuit register. Currently, the only cipher type specified is no cipher. Only 00. For prototypes, the network interface 105 would not be required to do anything with these bits.

The Network Interface Bus 101 (NI-Bus) signals are described below.

The data bus 201 has eight lines represented by ND0 to ND7. These eight three-state, bidirectional lines are the paths for the transfer of data between the network interface 105 and the peripherals connected to the NI bus 101.

The control bus 203 has eight lines designated NC0 to NC7, and these eight three-state output lines are NI.
For address / command devices connected to bus 101.

The output signal on the control clock (CCLK) line 427, when high, indicates that there is valid control information on the control bus 203.

The signal on the data clock (DCLK) line 419, when high, indicates that there is valid data on the NI data bus 201. The device that drives the NI data bus 201 is responsible for driving this signal.

The input signal of the packet start (PS) 417 becomes high level and stays high level while the data is transmitted from the peripheral device. The signal 417 goes low after the end-of-packet 421 signal goes low. The device that drives the data bus 201 drives the packet start signal 417.

The packet end (PE) 421 output signal goes high to indicate to the peripheral that all valid packet data has been received and the extra data bytes, if any, can be transmitted. Signal 421 goes low when all additional bytes have been received. The signal goes high when a maximum packet size or CRC error occurs.

The timing specifications of the processor bus signals are shown in FIGS. 11 to 17.

FIG. 11 shows the timing of network interface control. Devices on the control bus are controlled by the control bus (NIC0-
Control bus crack (NICC)
LK) read from low to high transition. This information is
Used to address a particular device on the NI bus and determine whether that device drives or listens to the data bus. One bit in each byte is whether the byte is an address byte or a command byte (drive or listen)
Used to determine

FIG. 12 shows the timing of data transfer when there is no additional byte from the device to the network interface. If the device is commanded to drive the data bus and has the information to send to the network interface, the device drives packet start (PKTST) low. At the same time, data is sent to the data bus (NID0-7). When the data on the data bus is valid,
The device drives NIDCLK from high to low to instruct the network interface to read the information. This operation continues until the network interface drives the end of packet (PKTEN) from high to low while NIDCLK is low. When the end of packet transitions from low to high, the device drives packet start from low to high and does not drive the bus thereafter.

FIG. 13 shows the timing of data transfer with additional bytes from the device to the network interface. The transfer of information from the device to the network interface is the same until the end of packet transition to low in FIG. If the packet end (PKTEN) remains low during the next low-to-high transition of the NI Bus Clock (NIBCLK), the device sends an extra byte to the network interface. The validity of the information on the data bus is further dictated by NIDCLK. The device is
Continue supplying additional bytes until the end-of-packet signal transitions from low to high. The device drives a packet start from low to high and does not drive the bus thereafter.

FIG. 14 shows the timing of data transfer from the network interface to the device. When the device is commanded to listen to the data bus via the control bus, the network interface sends data on the data bus (NID0-7). When the information is valid, the network interface drives NIDCLK from high to low, instructing the device to read the information. The network interface continues this process until all required information has been transferred to the device. After the transfer ends, the network interface does not drive NIDCLK.

FIG. 15 shows the timing of data transfer when there is a maximum packet size error from the device to the network interface. Network interface
When it determines that there is a maximum packet size error due to the fact that the packet length in the packet header is larger than the maximum packet size stored in the virtual circuit, the network interface stops forwarding the packet. This is done by the network interface driving packet end (PKTEN) low while the data clock (NIDCLK) is low in the first byte of the address field of the packet. This indicates that the device should no longer drive the data bus due to the presence of an error. After confirming the low-to-high transition at the end of the packet, the device drives packet start (PKTST) high.

FIG. 16 shows the timing of data transfer when a CRC error from the device to the network interface is involved. CRC of header information for network interface
Check. When it is determined that the CRC error is present, the network interface stops forwarding the packet. This is because the data clock (NIDCLK) is low in the fourth byte of the information field of the packet,
Network interface ends packet (PKTEN)
Is driven low. This indicates that the device should no longer drive the data bus because a CRC error was present. After confirming the low-to-high transition at the end of the packet, the device drives packet start (PKTST) high.

FIG. 17 shows the timing of data transfer when an address error occurs from the device to the network interface. An address error occurs when the address in the packet header does not match the address stored in the network interface address table. This means that while the data clock (NIDCLK) is low in the second byte following the byte at the address where the mismatch occurred (time delay of 2 bytes in address comparison), the network interface outputs the end of packet (PKTEN). It is done by driving. This indicates that the device should no longer drive the data bus because of an address error. After confirming the low-to-high transition at the end of the packet, the device drives packet start (PKTST) high.

The maximum rise and fall times for CCLK427, DCLK419, PS417, and PE421 are 5 nanoseconds. Rise and fall times are from 10% to 90%. All times are typical unless otherwise noted.

While various embodiments of packet / high speed packet switches for voice and data according to the present invention have been described herein, the scope of the invention is defined by the following claims.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Joanson Lisa Bee 60004, Arlington Heights, North Chicago Avenue, Illinois, USA 912 (72) Inventor Freeberg Thomas A, Arlington, 60004, Illinois, USA・ Heights, North Belmont Avenue 416 (56) References JP-A-60-23554 (JP, A) JP-A-63-174451 (JP, A)

Claims (10)

(57) [Claims] 1. A network interface bus (101).
A communication system comprising a network interface (NI) (105) coupled to at least one peripheral device via a network, wherein said network interface bus is a control bus (203) for communicating control packets, A data bus (201) for communication is provided, and the network interface bus further includes a packet start line (417) and a data clock line (41).
9), packet end line (421), control bus line (20
3) and a control clock line (427), said network interface being a processor bus (103)
A communication system coupled to a control processor (107) via. 2. The network interface (105)
Are coupled to the data bus (201), the packet start line (417), the data clock line (419), and the packet end line (421) to evaluate and act on the header of an incoming packet. Input means (405) for determining what to do and addressing an interface device, coupled to said control bus line (203) and said control clock line (427) for outputting packets from said network interface and said control Output means for outputting control information to the bus (40
7), coupled to the control bus line (203), the control clock line (427), the input means (405) and the output means (407), for decoding commands
Bus decoding means (409), memory access control means (403) for allocating memory access to the input means, output means, and processor interface means (207) coupled to the input means and the output means, the memory access control means Processor interface means (207) coupled to the control processor for network interface with the network interface, and memory means (111) coupled to the input means, the output means and the processor interface means. The system of claim 1 in the range. 3. Input means for evaluating a header of an incoming packet, means for loading said header and determining routing in response to receiving a packet start indication along with a data clock, and said routing. 3. The system of claim 2 including means for loading the information field of said packet into said memory in response to said decision. 4. The output means includes means for outputting a packet to the at least one peripheral device on the data bus and means for outputting control information on the control bus. The system described in the section. 5. The NI bus decoding means is for listening to addresses and commands on the NI bus, for decoding all commands having a broadcast or network interface address, and for the input means. Claim: Claims including means for providing control to indicate when to receive data over the data bus, and means for providing control to the output means to indicate when to drive the data bus. The system according to item 4. 6. The system of claim 5 wherein said memory access control means includes means for allocating an appropriate number of NI memory accesses to said input means, said output means and said processor interface means. 7. The system of claim 6 wherein said processor interface means includes means for interfacing between said control processor and said network interface, said processor interface means further comprising NI base register means. . 8. The memory means comprises means for providing the memory required by the network interface, including memory for the packets and memory for registers required for routing and addressing. The system of claim 7 including. 9. The memory means (111) further comprises virtual circuit register means (501), address register means (503),
Processor data means (505), control buffer means (50
9), and a memory section with data buffer means (507), said virtual circuit register means being used to determine where in said memory means (111) a packet should be stored, Address register means allow the device to have multiple addresses of multiple types, said processor data means enable storage for all incoming packets, and said control buffer means controls said data bus (201). 9. A system as claimed in claim 8 which enables storage for address / command bytes used for, the data buffer means being used for buffering frames. 10. A plurality of devices coupled to each other via a bus, said devices communicating with each other by sending and receiving packets by said bus, each packet comprising a circuit identification (ID) field, A method for processing a packet it receives via said bus in a communication system comprising a packet length field, an address type field, an address length field, an address, a frame check sequence field, an information field, a) determining the appropriate address of an address register in memory using the contents of the address type field; (b) reading from the memory how many bytes of the determined address using the contents of the address length field. (C) In the step (b), Comparing the content of the byte read from the memory with the content of the address field, (d) whether the packet is being sent to the device based on at least a partial comparison in step (c). A method of processing a packet in a communication system comprising: determining.