JPH0750648A - Multiple channels asynchronous signal multiplex transmitter - Google Patents

Abstract

PURPOSE:To enable the multiplexing of plural asynchronous signals without enlarging the scale of a device. CONSTITUTION:This device is provided with a data buffer 101 storing and transmitting a multiple channels asynchronous signal, a writing address generation circuit 102 designating the area of the data buffer where the signal of each channel of this multiple channels asynchronous signal is stored and a reading address generation circuit 103 generating a reading address value for dividing the multiple channels asynchronous signal stored in the data buffer into time slots each channel and transmitting the slots A pulse showing the presence or absence of read data and a pulse showing the reference phase of the time slots are outputted at the same time of a a data output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel asynchronous signal multiplex transmission device for transmitting time-series data such as multi-channel moving images and sounds.

[0002]

2. Description of the Related Art In recent years, video sources have become abundant, and CAT
Video services such as V are being actively provided. In addition, with the rapid progress of video and audio signal compression technology and the progress of international standardization (MPEG, etc.), the improvement of storage media capacity, and the spread of digital communication represented by ISDN, moving image information by digital communication network Services are becoming feasible.

However, the bit rate of the band-compressed video signal is not always constant, and in order to multiplex multi-channel video signals, a configuration as shown in FIG. 5 has been conventionally considered. First, a plurality of signal sources 50 having different transmission sources
The respective outputs of 1-1 to 501-n are respectively input to the data buffers 502-1 to 502-n, and the outputs of the data buffers 502-1 to 502-n are switched by the switching circuit 50.
Input to 5.

The switching circuit 505 includes each signal source 501-.
Control circuit 50 having a transmission source different from 1 to 501-n
4, each data buffer 502-1-5
By multiplexing the data stored in 02-n and the synchronization signal output from the synchronization signal generation circuits 503-1 to 503-n, a plurality of asynchronous signals can be multiplexed. Alternatively, the data buffers 502-1 to 50-5
The output of 02-n is packetized and packet-multiplexed, thereby realizing the multiplexing of asynchronous signals of a plurality of channels.

[0005]

However, according to this conventional method, when the signal sources 501-1 to 501-n are multiplexed, the data buffers 502-1 to 502-n have the number of signal sources (in this case, Only n) are needed. In addition, the number of signal lines from the signal sources 501-1 to 501-n to the data buffers 502-1 to 502-n and the number of signal lines from the data buffers 502-1 to 502-n to the switching circuit 505 are multiplexed. As the number of channels to be converted increases, the number of channels increases and the scale of the transmission device increases.

The present invention has been made in view of the above problems, and an object thereof is to realize multiplexing of asynchronous signals of a plurality of channels without increasing the scale of the apparatus.

[0007]

In order to achieve the above object, a multi-channel asynchronous signal multiplex transmission apparatus of the present invention comprises:
One data buffer for storing and sending a multi-channel asynchronous signal, a write address generating circuit for designating an area of the data buffer in which a signal of each channel of the multi-channel asynchronous signal is stored, and a multi-buffer stored in the data buffer. A read address generation circuit that generates a read address value for transmitting a channel asynchronous signal divided into time slots for each channel, a data enable signal generation circuit that outputs a pulse indicating the presence or absence of read data, and a time slot It is configured by a reference signal generation circuit that outputs a pulse having a reference phase.

[0008]

According to the present invention, one data buffer area is divided for each channel, asynchronous data of each channel is stored in each area, and the stored data is divided into time slots for each channel. To send. In addition, by occasionally reading data (dummy data) other than the data in each channel area of this data buffer, and simultaneously outputting a pulse indicating the presence or absence of read data by the data enable generation circuit, a multi-channel asynchronous signal with a simple configuration can be obtained. Is to be multiplexed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multi-channel asynchronous signal multiplex transmission apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a multi-channel asynchronous signal multiplex transmission apparatus according to an embodiment of the present invention.

In FIG. 1, 101 is a data buffer for storing and sending multi-channel asynchronous signals, and 102 is a write address value for designating an area of the data buffer 101 in which the signals of each channel of the multi-channel asynchronous signals are stored. Write address generation circuit for generating, 10
Reference numeral 3 is a read address generation circuit that generates a read address value for dividing the multi-channel asynchronous signal stored in the data buffer 101 into time slots for transmission for each channel, and 104 is a read output of the data buffer. A data enable signal generation circuit that outputs a pulse indicating the presence or absence of data, and a reference signal generation circuit 105 that outputs a pulse that becomes the reference phase of the time slot.

Further, 121 is a multi-channel asynchronous signal input terminal, 122 is a multi-channel asynchronous signal output terminal, 1
Reference numeral 23 is a reference signal input terminal, 124 is a data enable signal output terminal, and 125 is a reference signal output terminal. The write address value generated by the write address generation circuit 102 and the read address value generated by the read address generation circuit 103 are stored in a data buffer. 101 is input. Further, the read address value generated by the read address generating circuit 103 is also input to the data enable signal generating circuit 104 and the reference signal generating circuit 105.

The operation of the multi-channel asynchronous signal multiplex transmission device configured as described above will be described below with reference to FIG.

First, in FIG. 1, an input multi-channel asynchronous signal is input from the multi-channel asynchronous signal input terminal 121. At the same time, the input reference signal is input from the reference signal input terminal 123. This input reference signal is a plurality of pulses indicating the channel number, the number of data, and the beginning of data of the input multi-channel asynchronous signal. When this input reference signal is input to the write address generation circuit 102, the write address generation circuit 102 outputs the write address value of the area of the data buffer 101 in which the signal of each channel should be stored, and the input multi-channel asynchronous signal. Are stored in the respective areas of the data buffer 101. The write address value output from the write address generation circuit 102 is the read address generation circuit 103.
Is also entered.

On the other hand, the read address generation circuit 103
Generates a read address value for dividing the multi-channel asynchronous signal stored in the data buffer 101 into time slots for transmission for each channel. At this time, the write address output from the write address generating circuit 102 is generated. The amount of data written in each channel is detected by the value, and a read address value for smoothing and outputting the data is generated.

That is, data (dummy data) other than the data in the area of each channel of the data buffer 101 is occasionally read. The read address value at this time is a read address value unrelated to the data, and dummy data (no data) exists in the time slot of that channel.

Next, the data enable signal generation circuit 10
Reference numeral 4 is connected to the output of the read address generation circuit 103, detects the read address value generated by the read address generation circuit 103, and outputs a data enable signal indicating the presence or absence of data. This data enable signal distinguishes data from dummy data.

The reference signal generation circuit 105 outputs to the read address generation circuit 103 a reference signal (a signal indicating the first channel) serving as a reference for the time slot. The read address generation circuit 103 generates a read address value by this reference signal. The reference signal generation circuit 105 can be easily realized by an n-ary counter when multiplexing n-channel data.

The read address generating circuit 103 and the data enable signal generating circuit 104 will be described with reference to FIG.

FIG. 2 shows a read address generating circuit 10 in the multi-channel asynchronous signal multiplex transmission apparatus of this embodiment.
3 is a block diagram of the data enable signal generation circuit 104 and 201, 201 is a smoothing circuit, 202 is an address counter, 211 is a write address input terminal, 2
Reference numeral 12 is a reference signal input terminal, 213 is a read address output terminal, and 214 is a data enable signal output terminal.

The operation of the present embodiment having the above-described structure will be described. First, the address counter 202 always outputs the read address at a constant speed, but the write address is asynchronous with the read address. Here, the smoothing circuit 201 needs to match the numbers of data for writing and reading. Therefore, the smoothing circuit 201 grasps the number of data from the write address value input from the write address input terminal 211, and outputs the pulses corresponding to the insufficient number of writes for reading within the period.

This pulse is a data enable signal that absorbs the difference between the number of written data and the number of read data, and is output from the data enable signal output terminal 214 to the outside. The data enable signal is preferably distributed in the smoothing circuit 201 in consideration of buffering in a device connected next to the multi-channel asynchronous signal multiplex transmission device.

Next, when the data read is not performed by inputting the data enable signal from the smoothing circuit 201 to the count enable terminal of the address counter 202 (when the data enable signal = Low), the address counter 202 outputs. It holds the read address value of. The read data at this time is dummy data.

The reference signal input from the reference signal input terminal 212 serves as a reference for the above-mentioned time slot (showing the first channel), and the smoothing circuit 201 and the address counter 202 operate with this signal as a reference. To do.

Further, in FIG. 1, the write address generation circuit 102 and the read address generation circuit 103 have the same address map, and the channel designation circuit 10 is provided.
By providing 6, the write address generation circuit 10
The area of each channel of the data buffer 101 determined by the write address value generated by 2 and the time slot for each channel of the multi-channel asynchronous signal determined by the read address value generated by the read address generation circuit 103 are externally provided. You can specify more. FIG. 3 shows a conceptual diagram of the address map.

In FIG. 3, the address map shows the area of the data buffer. First, in FIG.
From the designation signal input terminal 126, the channel designation signal indicating the allocation of the data buffer area and the time slot for writing the signal of each channel is provided to the channel designation circuit 10.
6 is input. The channel designation circuit 106 has a memory, holds information for the channel designation, and notifies the write address generation circuit 102 and the read address generation circuit 103 of the area of the data buffer 101 for each designated channel. It also notifies the read address generation circuit 103 of the time slot allocation of the read data for each channel.

The write address generation circuit 102 generates a write address for writing the signal of each channel in the area indicated by the address map, and the read address generation circuit 103 outputs the write address value from the address map and the write address generation circuit 102. Thus, a read address is generated according to the area where the signal of each channel is stored and the designated time slot.

The address map can be freely reorganized by sending a channel designation signal from the designation signal input terminal 126 to the channel designation circuit 106 at any time, and the time slot of the read data of the data buffer 101 can be flexibly changed. Can be set arbitrarily.

Finally, FIG. 4 is a conceptual diagram of input / output signals in the multi-channel asynchronous signal multiplex transmission apparatus of this embodiment. 401 is a data buffer, 421 is an input multi-channel asynchronous signal, 422 is an output multi-channel asynchronous signal, 424 is an output data enable signal, and 425 is an output reference signal.

The input multi-channel asynchronous signal 421 of FIG.
Is a form of the input multi-channel signal, and the data of each channel is input in bursts, and the data rates thereof do not match and are asynchronous. The area of the data buffer 401 is divided for each channel. The output multi-channel asynchronous signal 422 is output from the data buffer 401 after being divided into time slots for each channel. The output data enable signal 424 indicates that data is present at the High level, Lo
The w indicates that there is no data (there is dummy data), and the output reference signal 425 is a pulse representing the first channel.

As described above, according to this embodiment, the data buffer 10 for storing and transmitting the multi-channel asynchronous signal.
1, a write address generation circuit 102 for designating an area of the data buffer 101 in which the signals of the respective channels of the multi-channel asynchronous signal are stored, and the data buffer 1
A multi-channel asynchronous signal stored in 01 is divided into time slots for each channel and transmitted, and a read address generating circuit 103 for generating a read address value is detected. By providing the data enable signal generation circuit 104 that outputs the indicated pulse and the reference signal generation circuit 105 that detects the read address value and outputs the pulse that indicates the reference phase of the time slot, a multi-channel asynchronous signal can be generated with a simple configuration. Can be multiplexed.

Although the signals processed in this embodiment are not particularly mentioned, multi-channel asynchronous operation can be easily performed by the same processing regardless of whether the data is serial data or data in a bus format of several bits. The signals can be multiplexed. Further, the multi-channel asynchronous signal written in the data buffer may be a signal including a band-compressed video signal and audio signal.

[0032]

As described above, according to the present invention, one data buffer for storing and sending multi-channel asynchronous signals,
A write address generation circuit that specifies the area of the data buffer where the signals of each channel of this multi-channel asynchronous signal are stored, and the multi-channel asynchronous signal that is stored in the data buffer is divided into time slots for each channel and sent out. To generate a read address value, a data enable signal generation circuit that detects the read address value and outputs a pulse indicating the presence or absence of read data, and outputs a pulse that is the reference phase of the time slot. By providing the reference signal generating circuit, it is possible to multiplex the asynchronous signals of multiple channels with a simple configuration, and it is possible to realize a low-cost device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multi-channel asynchronous signal multiplex transmission device of the present invention.

FIG. 2 is a block diagram showing a read address generation circuit and a data enable signal generation circuit of the same embodiment.

[Figure 3] Conceptual diagram of address map

FIG. 4 is a conceptual diagram of input / output signals of the same embodiment.

FIG. 5 is a block diagram of a conventional multi-channel asynchronous signal multiplex transmission device.

[Explanation of symbols]

 101 data buffer 102 write address generation circuit 103 read address generation circuit 104 data enable signal generation circuit 105 reference signal generation circuit 106 channel designation circuit

Claims (4)

[Claims] 1. A data buffer for storing and transmitting a multi-channel asynchronous signal, and a write address for generating a write address value for designating an area of the data buffer in which a signal of each channel of the multi-channel asynchronous signal is stored. A generator circuit, a read address generator circuit that generates a read address value for transmitting the multi-channel asynchronous signal stored in the data buffer by dividing it into time slots for each channel, and an output of the data buffer. A data enable signal generation circuit that outputs a pulse indicating the presence or absence of certain read data;
A multi-channel asynchronous signal multiplex transmission device, comprising: a reference signal generation circuit that outputs a pulse having a reference phase of the time slot. 2. A data buffer area determined by a write address value generated by a write address generation circuit and a time slot for each channel of a multi-channel asynchronous signal determined by a read address value generated by a read address generation circuit. 2. The multi-channel asynchronous signal multiplex transmission device according to claim 1, further comprising a channel designating circuit for designating. 3. The multi-channel asynchronous signal multiplex transmission device according to claim 2, wherein the write address generation circuit is composed of a smoothing circuit and an address counter. 4. The multi-channel asynchronous signal multiplex transmission apparatus according to claim 3, wherein the multi-channel asynchronous signal written in the data buffer comprises band-compressed video signals and audio signals.