JP2868026B2 - Multiplexer for asynchronous transfer mode and test apparatus therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous transfer mode (ATM).
The present invention relates to a multiplexing device in a system and a test device for its self-diagnosis.

[0002] Conventional circuit switching system (ST for ATM
M; referred to as a synchronous transfer mode), a time-division multiplexing bus (TD) is used to efficiently achieve synchronous multiplexing and reduce the number of connection lines between units.
M bus).

[0003] The present invention relates to an ATM multiplexer and a test apparatus for self-diagnosis using the TDM bus.

[0004]

2. Description of the Related Art FIG. 9 is a timing chart showing an example of assignment of a TDM bus in the case of STM. TDM
The bus function is divided into a number of time slots by the TDM bus clock (column (a)), and each unit connected to the TDM bus recognizes each time slot with reference to the frame pulse (column (b)). , And exchange data.

In the case of STM, one time slot is assigned to each channel for each of the uplink (from each terminal to the network) and the downlink (from the network to each terminal).
TS1 to TSn are allocated, and data of one byte is exchanged. For uplink, multiplexing is performed by successively reading data output from each channel to the bus sequentially. For downlink, multiplexed data is continuously output to predetermined time slots, and each channel is Demultiplexing is performed by reading the data of the assigned time slot.

If such a usage form of the TDM bus, that is, the assignment of the time slot is applied to the ATM as it is, the configuration shown in FIG. 10 can be considered.

In the ATM system, label multiplexing or statistical multiplexing is performed in units of fixed-length (for example, 53 bytes) cells including labels. However, conventionally, since each channel is assigned one time slot to one frame, the cell multiplexing unit 160, which has received the data assembled in the cell by the cell assembling unit 140 via the TDM bus 100, prepares data for one cell. After the data is stored in the shared memory 162, the data must be multiplexed in the multiplexing circuit 166. The cell synchronization circuit 164 finds the head of the cell from the data read one byte at a time from the TDM bus 100,
This circuit controls writing to the memory 162.

[0008]

As described above, if the time slot allocation of the TDM bus employed in the conventional STM system is applied to the ATM system multiplexer as it is, the cell multiplexing unit 160 will However, there is a problem that a memory having a length of one cell is required, and as the number of accommodated channels increases, the scale of hardware increases.

Therefore, an object of the present invention is to provide an AT which utilizes a TDM bus and has a relatively simple hardware configuration.
An object of the present invention is to provide a multiplexer for M.

It is another object of the present invention to provide a test apparatus capable of self-diagnosing such a multiplexing apparatus.

[0011]

FIG. 1 is a block diagram showing the principle of an ATM mode multiplexer according to the present invention, and FIG. 2 is a timing chart for explaining the assignment of a TDM bus.
The column (a) shows the TDM bus clock, the column (b) shows the frame pulse, and the column (c) shows the bus assignment. In the figure, a multiplexing device of the present invention includes a time division multiplexing bus 10 for transmitting data in each of m time slots in one frame defined with reference to a frame pulse FP generated at a predetermined time interval. , By generating the flag FLG once every n frames, the frame numbers FLM1 to FLMn from 1 to n based on the flag are generated.
And a plurality of upstream data transmitting means 14, at least some of which are different frame numbers, and have a common position with respect to the frame pulse FP, and are continuously assigned times. Slot CH
In 1-up to CHn-up, a plurality of uplink data transmitting means 14 for transmitting uplink data to the time division multiplex bus 10 and time slots (CH1-up to CHn-up) respectively assigned to the plurality of uplink data transmitting means 14. CHn-up), characterized by comprising upstream data multiplexing means 16 for sequentially reading out valid upstream data on the time division multiplex bus 10 and multiplexing the upstream data.

It is preferable that the plurality of upstream data transmitting means 14 be configured to convert the upstream data into fixed-length cells including labels for identifying a path and a destination, and transmit the fixed-length cells to the time division multiplex bus 10.

Further, the multiplexing device transmits multiplexed downlink data to the time division multiplex bus 10 in the time slot CHi-down continuously allocated to a predetermined position regardless of the frame number. Downlink data transmission means
18 and a plurality of downlink data separating means 20 for reading out downlink data on the time-division multiplex bus 10 in the time slot CHi-down and taking in only those which match the own label. It is.

FIG. 3 is a diagram showing the principle of the configuration of a test apparatus according to the present invention. FIG. 4 is a view for explaining the assignment of a TDM bus, wherein (a) shows a TDM bus cloak, and (b) shows a frame. The pulse, column (c), shows the bus assignment. In the figure, a test apparatus for an ATM multiplexing apparatus according to the present invention comprises a loopback path provided between an uplink data transmitting means 14 and a downlink data separating means 20 to be tested.
22, a transmission prohibition unit 24 for prohibiting transmission of downlink data by the downlink data transmission unit 18 in the frame of the specific frame number FLMn, and the downlink data transmission unit 18 in the frame of the specific frame number FLMn. In the time slot P-IN, a test pattern output unit 26 that outputs a test pattern including a label of the downlink data separation unit 20 to be tested to the time division multiplex bus 10,
Of the time slots CH1-up to CHn-up allocated to the upstream data transmitting means 14, the time division is performed in the time slot P-OUT in the frame of the frame number allocated to the upstream data transmitting means 14 to be tested. Multiplex bus 10
A pattern checking means for reading and checking the above data.

[0015]

When the valid uplink data on the predetermined time slots CH1-up to CHn-up is sequentially read out by the uplink data multiplexing means 16, statistical multiplexing is achieved by itself, and the uplink data multiplexing means 16 performs Is simple because a memory for one cell is sufficient. Note that FIG.
In FIG. 4, the flag FLG is shown as being transmitted to the time division multiplex bus 10 in a specific time slot. However, even if the flag FLG is supplied on a separate signal line similarly to the frame pulse FP, The good thing is, of course.

If the upstream data transmitted by the transmission data transmitting means 14 is a fixed-length cell including a label, label multiplexing in ATM is achieved.

For the downlink data, demultiplexing is achieved by the downlink data transmitting means 18 and the downlink data separating means 20.

In configuring a test apparatus for a multiplexing apparatus having this configuration, it is necessary to test a specific channel without affecting other channels. In other words, since the time slot CHi-down is commonly used for each channel for downlink data, simply inserting a test pattern into this time slot causes collision with data of another channel, resulting in an instantaneous interruption. Therefore, it is possible to make a test by inserting the test pattern labeled with the channel to be tested in this position so that the data is not output from the downlink data transmitting means 18 to the bus at the specific frame number as described above. Becomes

[0019]

FIG. 5 is a block diagram showing an ATM type multiplexing apparatus according to a first embodiment of the present invention, in which only a portion relating to uplink data is shown.

The multiplexing device 400 comprises six units of two terminal interfaces 144, 145, two cell processing units 142, 143, a cell multiplexing unit 170, and a line interface 174. Data transmission and reception are performed via the TDM bus 100.

The terminal interface 144 receives data from the terminal device 300 on channels 1 to 40, and the terminal interface 145 receives data from the terminal device 30 on channels 41 to 80.
Data from 0 is input. The data input from the terminal device 300 includes audio data, image data, digital data based on the HDLC procedure, and the like. The terminal interfaces 144 and 145 perform encoding or level conversion of the input data, and perform cell processing units 142 and 143 via the TDM bus 100 in the assigned time slots.
Respectively.

The cell processing units 142 and 143 have a predetermined length of data from the terminal interfaces 144 and 145, which are only valid data, that is, voice data except for silence parts and HDLC data except for invalid data. Break,
Cells are assembled with labels for identifying destinations and routes and stored in the memories 146 and 147 for each channel. The output control unit 148 counts the time slot number and the frame number based on the frame pulse, the clock of the TDM bus 100 and the flag on the bus, and stores the data in the memory 146 or 147 of the channel corresponding to the assigned time slot and frame number. TDM bus 10 if available
0 Performs control to output on top.

The flag output circuit 120 provided in the cell multiplexing unit 170 outputs the above-described flag in a predetermined time slot at a rate of once every forty times, and uses it as a reference for the frame number. The memory 172 has a capacity of one cell, sequentially reads and stores valid data in time slots allocated to the cell processing 142 and 143, and outputs the data to the line interface 174 via the TDM bus 100. By doing so, label multiplexing is performed.

FIG. 6 shows the TD in the multiplexer 400 of FIG.
FIG. 3 is a diagram for explaining allocation of a time slot of the M bus 100. It is divided into 512 time slots by the frame pulse FP, and time slot A (time slot 1) is assigned as a flag. In the time slot A, 00H is output from the flag output circuit 120 only once in 40 times, and the other times are not output.
Becomes When 00, the frame is defined as frame 1 (FLM1), and frames 2 to
40 (FLM2 to FLM40) are defined.

Time slot B (time slots 3 to 5)
In 5), data from the cell assembling section 142 to the cell multiplexing section 172 is allocated, and channels 1 to 40 (CH1 to CH40) are allocated to FLM1 to FLM40, respectively. The data from the cell assembling unit 143 to the cell multiplexing unit 172 is allocated to the time slot C (time slots 101 to 153), and the channels 41 to 41 are assigned to the FLM1 to FLM40, respectively.
Channel 80 (CH41 to CH80) is allocated.

In the time slot D, data from the terminal interfaces 144 and 145 to the cell assembling units 142 and 143 are allocated. The allocation of this area may be a conventional method that does not depend on the frame number. Cell multiplexing section in time slot E
Data from 170 to line interface 174 is allocated.

Although not shown, a time slot is also allocated for downlink data.

FIG. 7 is a diagram showing the configuration of a test apparatus for self-diagnosis according to a second embodiment of the present invention incorporated in the multiplexer shown in FIG. In this figure, the down data is also indicated by an arrow. In the figure, in order to test the channel 2 as an example, the channel 2 is provided with a return path 220 between the input terminal and the output terminal of the terminal interface 144.

Stop control circuit provided in cell multiplexing section 170
240, as described in more detail below, to avoid collisions with data from other channels during testing on a particular channel.
TDM bus 100 in a frame of a specific frame number
Control to stop output to

A pattern generation circuit 260 provided in the test unit 290 is a circuit for attaching a label of a channel to be tested to a test pattern and outputting the label to a TDM bus, and a control circuit 262 stores a time slot number and a frame number. The output of the pattern generation circuit 260 is controlled by counting. The pattern check circuit 280 is a circuit for checking a pattern that has returned after looping back.

FIG. 8 is a diagram for explaining the operation of the test apparatus of FIG.

Before describing the operation of the test apparatus, the transmission and reception of downlink data between cell multiplexing section 170 and cell processing sections 142 and 143 will be described with reference to FIGS. Cell multiplexing section 170 has time slots 199-251 and 297-349 (denoted by CHi) allocated according to the cell length.
, Regardless of the frame number, T
Output to DM bus 100. The cell processing units 142 and 143 read the cells in the time slots 199 to 251 and 297 to 349, and if the channel corresponding to the channel identification code in the label is contained in the cell processing unit, fetch it. , And restore data by sorting to the corresponding channel.

At the time of the test, the stop control circuit 240
For example, time slot 297 to 349 of frame 40 (FLM40)
Output to is stopped. Then, a test pattern generated by the pattern generation circuit 260 and labeled with a test target (channel 2 in this example) is inserted at this position. The cell processing unit 142 picks up this and sends it to channel 2
Is written to the time slots 3 to 55 of the frame 2 (FLM2) via the terminal interface 144, the return path 220, the terminal interface 144, and the cell processing unit 142. The pattern check circuit 280 picks up this and determines whether or not it has been turned back normally.

[0034]

As described above, according to the present invention,
A multiplexing apparatus for an ATM system having a relatively simple configuration and a test apparatus therefor is provided, which effectively utilizes a TDM bus used in a conventional multiplexing apparatus of an STM system.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of a multiplexing device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the device of FIG. 1;

FIG. 3 is a principle configuration diagram of a test device for a multiplexing device according to the present invention.

FIG. 4 is a timing chart for explaining the operation of the device in FIG. 3;

FIG. 5 is a block diagram of an ATM multiplexer according to a first embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the device of FIG. 5;

FIG. 7 shows a test device for a multiplexing device according to a second embodiment of the present invention.

FIG. 8 is a diagram for explaining the operation of the device of FIG. 7;

FIG. 9 shows a TDM in a conventional STM type multiplexer.
6 is a timing chart for explaining bus assignment.

FIG. 10 is a block diagram illustrating a configuration of a conventional ATM multiplexer based on TDM bus allocation.

[Explanation of symbols]

 10 time-division multiplex bus 12 flag transmission means 14 uplink data transmission means 16 uplink data multiplexing means 18 downlink data transmission means 20 downlink data separation means

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-196654 (JP, A) JP-A-4-196635 (JP, A) JP-A-4-207544 (JP, A) 39661 (JP, A) JP-A-56-30346 (JP, A) JP-A-55-5514 (JP, A) JP-A-63-190450 (JP, A) (58) Fields investigated (Int. ⁶ , DB name) H04L 12/28 H04J 3/00

Claims (4)

(57) [Claims] 1. m within a frame defined on the basis of a frame pulse (FP) generated at a predetermined time interval.
A time-division multiplex bus (10) for transmitting data in each of the time slots, and a flag (FLG) generated once every n frames, so that frames 1 to n based on the flag are used. Flag generating means (12) for defining numbers (FLM1 to FLMn) and a plurality of upstream data transmitting means (14), at least some of which have different frame numbers, and A plurality of uplink data transmitting means (14) for transmitting uplink data to the time division multiplex bus (10) in consecutively assigned time slots (CH1-up to CHn-up) having a common position; Time slots (CH1-up to CHn-u) respectively assigned to the plurality of uplink data transmitting means (14).
and p) an upstream data multiplexing means (16) for sequentially reading out valid upstream data on the time division multiplex bus (10) and multiplexing the upstream data. Multiplexer. 2. A plurality of upstream data transmitting means (14)
2. The multiplexing device according to claim 1, wherein the multiplexing device converts the upstream data into a fixed-length cell including a label for identifying a route and a destination, and transmits the fixed-length cell to the time-division multiplexing bus. 3. A time slot (CHi-down) continuously allocated to a predetermined position regardless of the frame number.
And a downlink data transmitting means (18) for transmitting the multiplexed downlink data to the time division multiplex bus (10), and a downlink on the time division multiplex bus (10) in the time slot (CHi-down). 3. The multiplexing apparatus according to claim 2, further comprising: a plurality of downlink data separating means (20) for reading data and taking in only a data which matches with its own label. 4. A test apparatus for a multiplexing apparatus according to claim 3, wherein a loopback path is provided between the upstream data transmitting means (14) and the downstream data separating means (20) to be tested. (22), transmission prohibition means (24) for prohibiting transmission of downlink data by the downlink data transmission means (18) in the frame of the specific frame number (FLMn), and transmission inhibition means (24) in the frame of the specific frame number (FLMn). The time slot (PI) assigned to the downlink data transmitting means (18)
In N), a test pattern including a label of the downlink data separating means (20) to be tested is transferred to the time division multiplex bus (10).
Of the test pattern output means (26) for outputting to the upstream data transmission means (14) and the time slot (CH1-up to CHn-up) allocated to the uplink data transmission means (14). A pattern checking means (28) for reading and checking data on the time-division multiplexed bus (10) in a time slot (P-OUT) in a frame of a given frame number. .