JP2944490B2 - Time slot allocation method for time division multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time slot allocating method for a time division multiplexing device, and more particularly to a time slot allocating method for a time division multiplexing device for allocating time slots of a time division multiplexing bus.

[0002]

2. Description of the Related Art Referring to FIG. 5, a conventional time slot multiplexing method of a time division multiplexing apparatus uses a designated time slot (hereinafter referred to as a time slot) of line data input through a downlink A-1 of a terminal line A. TS) is converted into parallel data in accordance with an internal reference clock and a frame pulse supplied from a time switch circuit 4 to be described later via a clock bus G, and the converted parallel data is input to the TS via a control bus D. The TS specified by the allocation information α is allocated and multiplexed on a time division multiplexing (hereinafter, referred to as TDM) transmission bus E, and the pre-assigned parallel multiplexed data input from the TDM reception bus F is described later. Time switch circuit 4
A channel interface circuit 101 which converts serial data into serial data in accordance with an internal reference clock and a frame pulse supplied from an external device via a clock bus G, allocates a designated TS, and outputs the assigned TS to an upstream line A-2 of a terminal line A; The serial data of the specified TS of the line data input through the downstream line B-1 of B is converted into parallel data in accordance with the internal reference clock and the frame pulse supplied from the time switch circuit 4 through the clock bus G to be described later. A TS specified by the TS allocation information β input through the control bus D is allocated and multiplexed to the TDM transmission bus E, and the TDM
The parallel multiplexed data to which a TS is assigned in advance from the receiving bus F is converted into serial data in accordance with a reference clock and a frame pulse supplied from the time switch circuit 4 through the clock bus G from the time switch circuit 4 to be described later. A line interface circuit 102 for allocating a TS and outputting the allocated TS to the uplink line B-2 of the trunk line B
And the serial data of the specified TS of the line data input through the downlink C-1 of the trunk line C is converted into parallel data according to the internal reference clock and frame pulse supplied from the time switch circuit 4 through the clock bus G to be described later. , And allocates a TS specified by the TS allocation information γ input through the control bus D to multiplex it on the TDM transmission bus E. Multiplexed data is converted into serial data in accordance with an internal reference clock and a frame pulse supplied from a time switch circuit 4 to be described later through a clock bus G, and a designated TS is allocated to the uplink C-line of the trunk line C.
2 supplies a reference clock and a frame pulse to the channel interface circuit 1 and the line interface circuits 2 and 3 to the channel interface circuit 1 and the line interface circuits 2 and 3 through the clock bus G.
The time switch circuit 104, which controls the line data of the specified TS on the TDM transmission bus E to be replaced with the specified TS on the TDM reception bus F under the control of the time slot replacement information δ input through Supply the TS allocation information α, β, and γ to each of the channel interface circuit 101 and the line interface circuits 102 and 103 through the control bus D, and transmit the time slot replacement information δ
And a control circuit 105 for supplying the data to the control circuit 04.

Further, referring to FIG. 6 in conjunction with FIG. 5, the channel interface circuit 101 and the line interface circuits 102 and 103 are respectively connected to the terminal line A, the trunk line B or the trunk line C. The serial data of the specified TS from the line is converted into parallel data according to the internal reference clock and frame pulse supplied from the time switch circuit 4 through the clock bus G, and the T input through the control bus D.
A multiplexing circuit 1000 for allocating a TS for multiplexing on a TDM transmission bus specified by the S allocation information
And the parallel data from the multiplexing circuit 1000
An output gate 1001 as an interface circuit for outputting to the transmission bus E, an input gate 1002 as an interface circuit for taking parallel multiplexed data from the TDM reception bus F into an internal circuit, and an input gate 100
The line data of the TS specified by the time slot allocation information input through the control bus D from the parallel multiplexed data fetched in Step 2 is supplied from the time switch circuit 4 through the clock bus G to the internal reference clock. And a multiplexing / demultiplexing circuit 1003 which converts the data into serial data according to the frame pulse, allocates a designated TS on each line, and outputs it to the terminal line A, the relay line B or the upstream line of the relay line C. Be composed.

More specifically, the control circuit 105 determines a TS number of each line data on the downlink of the terminal line A, the relay line B and the relay line C, and a TS number on the TDM transmission bus E.
Number, terminal line A, trunk line B and trunk line C
Number and TDM of each line data on the upstream line
The respective TS allocation information α, β, and γ for associating with the TS number on the reception bus F are multiplexed with the respective multiplexing circuits 1000 of the channel interface circuit 101 and the line interface circuits 102 and 103 through the control bus D. It is supplied to the separation circuit 1003. As a result, the multiplexing circuit 1000 of each interface circuit transmits the TS
T corresponding to the own circuit of each of the allocation information α, β and γ
T assigned on TDM transmission bus E by S assignment designation
S is multiplexed with each line data.

The control circuit 105 supplies TS switching information δ to the time switch circuit 104 through the control bus D. Thereby, the time switch circuit 104
Replaces the line data of each designated TS on the TDM transmission bus E with the designated TS on the TDM reception bus F. The multiplexed data on the TDM receiving bus F is
The demultiplexing circuit 1003 of each interface circuit demultiplexes the data according to the instruction of the TS allocation information from the control circuit 105, and divides the demultiplexed serial data into the TS corresponding to the uplink of each data line. It is sent along with it.

In the above description, the TDM transmission buses E and T
The operation of exchanging TS with the DM receiving bus F will be described with reference to the timing chart of FIG. 7 together with FIGS. The timing chart in FIG. 7 shows the flow in the case where a part of the line data of the serial data from the downstream line A-1 of the terminal line A is transmitted to the upstream line C-2 of the relay line C, and the flow of the relay line B In the case where the line data of a part of the serial data from the downlink B-1 is transmitted to the uplink C-2 of the trunk C, and the flow of the serial data from the downlink C-1 of the trunk C. The line data of this part is the uplink line B-2 of the relay line B.
And the flow when part of the serial data from the downlink C-1 of the trunk line C is transmitted to the uplink A-2 of the terminal line A. TDM transmission bus E and TDM reception bus F
The switching of TS between the time switch circuit 10
4 through. First, the flow of line data will be described. The serial line data from the terminal line A is transmitted to the multiplexing circuit 1 of the channel interface circuit 101.
000, the data is converted to parallel data.
It is allocated to the TS in the portion C on the transmission bus E and multiplexed. Next, the time switch circuit 104 replaces the line data of the TS portion of the C portion on the TDM transmission bus E with the TS portion of the E portion of the TDM receiving bus F in accordance with the command of the TS replacement information δ from the control circuit 105. Then, the demultiplexing circuit 1003 in the line interface circuit 103 demultiplexes the line data of the TS portion on the TDM reception bus F in accordance with the command of the TS allocation information γ from the control circuit 105 and converts the data from parallel data to serial data. Along with
The converted serial data is added to the uplink line C of the trunk line C.
-2 and transmit the TS. In this manner, the downlink line data from the terminal line A is switched by the time switch circuit 104 from the TS on the TDM transmission bus E to the TS on the TDM reception bus F, and
The same applies to the reverse case, that is, the case where the downlink line data from the trunk line C is transmitted in the uplink direction of the terminal line A, and the same applies to the downlink direction from the relay line B. The same applies to the case where the line data is transmitted in the upward direction of the trunk line C and the case where the downward line data from the relay line C is transmitted in the upward direction of the trunk line B, so that the description is omitted.

[0007]

In the conventional time slot multiplexing method of the time division multiplexing device, the position of the TS on the time division multiplexing bus can be freely changed. Even relay transmission data of a large unit that does not require complicated switching control such as being bypassed to the interface circuit passes through the time switch circuit, so the use efficiency of the time division multiplex bus is poor,
There was a problem that relay delay also increased.

[0008]

According to a time slot allocating method of a time division multiplexing apparatus according to the present invention, downlink line data from a transmission line is multiplexed to a designated time slot of a time division multiplex transmission bus. A plurality of multiplexing means provided for each of the transmission lines, and a specified time slot of the time-division multiplexed reception bus, the data of the specified time slot of the first multiplexed data multiplexed on the time-division multiplexed transmission bus. A time slot exchanging means for demultiplexing data of a designated time slot from the second multiplexed data on the time division multiplex receiving bus, and transmitting the data in an uplink direction corresponding to each of the plurality of transmission lines. In a time slot allocating method of a time division multiplexing device having multiplexing / demultiplexing means, the downlink line data from a certain transmission line is transmitted to another transmission line. When performing bypass transmission in the upstream direction of the line, the time slot on the time division multiplex transmission bus and the time division on the time division multiplex transmission bus or the time division Means for bypassing only on multiple receive buses
It is characterized by having .

Further, the time slot allocating method of the time division multiplexing apparatus according to the present invention is a time division multiplexing method for multiplexing / demultiplexing downlink data from a transmission line and transferring the multiplexed data to an uplink line of another line. In the time slot allocation method of the coding device, a communication for exchanging time slots between the downlink line data and the uplink line data is performed.
In the case of a line using ordinary means, the downlink line data of the transmission line is multiplexed into the first time slot on the time division multiplex transmission bus specified by the first time slot allocation information. wherein the time slot interchange means the downlink data multiplexed in the time division multiplexed bus is specified by the time slot interchange information
The downlink data exchanged from the first time slot on the time division multiplex transmission bus to the second time slot on the time division multiplex reception bus is demultiplexed in accordance with the second time slot allocation information, and the other line is demultiplexed. Of the line using a bypass means for not transferring the time slot between the downlink line data and the uplink line data as the uplink line data of the transmission line.
In this case, the downlink line data of the transmission line is
Third with multiplexing in the time slot, multiplexed other line in the time division multiplexed bus on division multiplexing receiving bus when it is specified in the time slot with allocation information
A plurality of line interface means for each line for multiplexing and demultiplexing line data in the downstream direction of the transmission line in accordance with the third time slot allocation information and bypass-transferring the transmission line in the upstream direction of the transmission line; Time slot switching means for replacing the downlink line data of a designated time slot on the time division multiplex transmission bus with a designated time slot on the time division multiplex reception bus according to the first, second and third time slots. Control means for outputting third time slot allocation information and supplying it to each of the plurality of line interface means, and outputting the time slot replacement information and supplying it to the time slot replacement means. Features .

Further, in the time slot allocating method of the time division multiplexing apparatus according to the present invention, the line interface means exchanges time slots between downlink line data and uplink line data of the transmission line. For
In the case of a line using the usual means, sometimes the downlink line data to be multiplexed to the first time slot on the time division multiplex transmission bus is transmitted to the time division multiplex transmission bus, and In the case of a line using bypass means for preventing the exchange of the time slot between the downlink line data and the uplink line data, multiplexing is performed on the first time slot on the time division multiplex transmission bus. A first selecting means for transmitting the downlink line data to be converted to the time division multiplexing reception bus, and a time slot for exchanging time slots between downlink line data and uplink line data of the transmission line . Use normal means
In the case of a line, the downstream line data for the demultiplexing to be transferred in the upstream direction is fetched from the time division multiplex receiving bus, and the downstream line data and the upstream line data are In the case of a line using bypass means for preventing the time slots from being exchanged,
In this case, there is provided a second selecting means for fetching, from the time division multiplex transmission bus, the downlink line data for multiplexing and demultiplexing which is transferred in the uplink direction .

[0011]

Next, the present invention will be described with reference to the drawings. Referring to FIG. 1 showing one embodiment of the present invention, a time slot allocating method of a time division multiplexing apparatus is as follows.
The serial line data input through the downstream line A-1 of the terminal line A is converted into parallel data in accordance with the internal reference clock and the frame pulse supplied from the time switch circuit 4 to be described later through the clock bus G and converted. TDM transmission bus E specified by TS allocation information a input to parallel data through control bus D
The above TS is allocated and multiplexed on the TDM transmission bus E, and the line data of the TS specified by the TS allocation information a is taken from the multiplexed data on the TDM reception bus F via the control bus D into its own circuit and multiplexed. It is separated and converted into serial data in accordance with an internal reference clock and frame pulse supplied from a time switch circuit 4 to be described later through a clock bus G, and the specified TS in the upstream line A-2 of the terminal line A is converted into the serial data. A channel interface circuit 1 for allocating and transmitting, and serial line data input through the down-link B-1 of the relay line B, and an internal reference clock and frame pulse supplied through a clock bus G from a time switch circuit 4 to be described later. Into parallel data according to A TS on the TDM transmission bus E specified by the TS allocation information b input to the data through the control bus D is allocated and multiplexed on the TDM transmission bus E, and the multiplexed data on the TDM reception bus F is used to control the data from the control bus. D, the line data of the TS specified by the TS allocation information b is taken into its own circuit, demultiplexed, and converted into serial data in accordance with the internal reference clock and frame pulse supplied from the time switch circuit 4 through the clock bus G to be described later. A line interface circuit 2 for converting the serial data and allocating a designated TS in an uplink line B-2 of the trunk line B to transmit the serial data; and serial line data input through a downlink line C-1 of the trunk line C Is an internal reference supplied from a time switch circuit 4 to be described later through a clock bus G. According to the lock and frame pulses, the data is converted into parallel data, and the converted parallel data is allocated to the TS on the TDM transmission bus E specified by the TS allocation information c input via the control bus D, and the TDM transmission bus E To the control bus D from the multiplexed data on the TDM reception bus F.
The circuit data of the TS specified by the TS allocation information c is taken into its own circuit, multiplexed and demultiplexed, and converted into serial data in accordance with the internal reference clock and frame pulse supplied from the time switch circuit 4 through the clock bus G to be described later. To the line interface circuit 3 for allocating the designated TS in the uplink line C-2 of the trunk line C to the serial data and transmitting the same, and to the channel interface circuit 1 and the line interface circuits 2 and 3 through the clock bus G. The reference clock and the frame pulse are supplied, and the line data of the specified TS of the multiplexed data on the TDM transmission bus E is controlled by the TS replacement information d input through the control bus D to the specified data on the TDM reception bus F. Times mentioned above to replace with TS Switch circuit 4, the TS allocation information a for the channel interface circuit 1, the TS allocation information b for the line interface circuit 2, and the TS allocation information c for the line interface circuit 3 through the control bus D. Control circuit 5 for supplying time slot exchange information d to time switch circuit 4
It is composed of

Still referring to FIG. 2, each of the channel interface circuit 1, the line interface circuit 2, and the line interface circuit 3 converts serial line data from the terminal line A or the downstream lines of the relay lines B and C into time. In accordance with the internal reference clock and frame pulse supplied from the switch circuit 4 via the clock bus G, the data is converted into parallel data on the TDM transmission bus E designated by the TS allocation information from the control bus D. A multiplexing circuit 10 for allocating a TS for multiplexing and outputting the multiplexed data, and a line data for multiplexing the output of the multiplexing circuit 10 controlled by a control signal e.
A transmission selector 11 for selecting transmission to the DM transmission bus E side or transmission to the TDM reception bus F side; and line data for multiplexing the output of the transmission selector 11 controlled by the control signal f. I / O gate 1 for selecting whether to multiplex on E or to take in the multiplexed line data from TDM transmission bus E to its own receiving side
2, and multiplexes the line data for multiplexing the output of the transmission selector 11 on the TDM reception bus F under the control of the control signal g, or receives the multiplexed line data from the TDM reception bus F An input / output gate 13 for selecting whether the data is to be taken into the device, a multiplexed line data taken into the device from the input / output gate 12 under the control of the control signal h, and a product from the input / output gate 13 to the device receiving device. And the selected multiplexed line data, and outputs the selected multiplexed line data, and the specified TS of the multiplexed line data from the receive selector 14 based on the TS allocation information from the control bus D. The line data is demultiplexed and converted from parallel data in accordance with the internal reference clock and frame pulse supplied from the time switch circuit 4 through the clock bus G. A multiplexing / demultiplexing circuit 15 which converts the serial data into a designated TS on each uplink and transmits the converted serial data to the multiplexing circuit 10 from the control bus D. When the TS allocation information is set for bypass on the TDM bus, a TS number register 16 for storing only the TS allocation information as a TS number;
And a TS number counter 17 for counting the number of TSs based on the internal reference clock and the frame pulse i supplied from the time switch circuit 4 from the time switch circuit 4, and the TS number stored in the TS number register 16 and the TS number counted by the TS number counter 17. And a TS number detection circuit 18 for detecting a match / mismatch.

Next, referring to FIG. 1 to FIG. 3 in detail, the multiplexing circuit 10 determines the designated TS on the trunk line or the terminal circuit according to the TS allocation information from the control bus D. The serial data is received and multiplexed and transmitted to a designated TS on the TDM transmission bus E. Use normal means for exchanging TS via time switch circuit 4
At the time of multiplex control in the case of a line , the TS assignment information is set only in the multiplexing circuit 10, and the output of the TS number detecting circuit 18 is always off. At this time, the transmission selector 11 and the input / output gate 12 are selected in the direction of the TDM transmission bus E.
Conversely, when the TS on the TDM transmission bus E is set for bypass and the TS is exchanged without passing through the time switch circuit 4, the TS number is stored in the TS number register 16 and the clock pulse in the device and The output of the TS number detection circuit 18 is turned on at the timing coincident with the count value of the TS number counter 17 counted by the frame pulse i, and the transmission selector 11 and the reception selector 14 and the input / output gates 12 and 13 are controlled. You.
That is, during the TS designated for bypass, the data from the multiplexing circuit 10 is not output to the TDM transmission bus E but is output to the TDM reception bus F.

Similarly, the demultiplexing circuit 15 receives the data of the specified TS on the multiplex bus according to the TS allocation information, and receives the data of the specified TS on the terminal line or the relay line.
Send to During normal demultiplexing control, the TS allocation information is set only in the demultiplexing circuit 15, and the output of the TS number detection circuit 18 is always off. At this time, the reception selector 14 and the input / output gate 13 are selected in the direction of the TDM reception bus F. Conversely, the TS on the TDM bus is
Is set in the TS number register 16, the T
At the timing when the S number is stored and coincides with the value of the TS number counter counted by the internal reference clock and the frame pulse, the output of the TS number detection circuit 18 is turned on, and the transmission selector 11, the reception selector 14, and the input
The output gate 12 and the input / output gate 13 are controlled. That is, during the TS designated for bypass, the demultiplexing circuit 15 inputs parallel data from the TDM transmission bus E.

FIG. 3 is a time chart showing the time relationship between the frame pulse supplied from the time switch circuit 4, the multiplexed data on the TDM bus, and the data on the line.
The signal flow will be described using this.

First, the flow of data in the case of a line using ordinary means will be described. The channel interface circuit 1 for terminating the terminal line A and the line interface circuit 3 for terminating the relay line C are set with normal TS allocation information from the control circuit 5, and the TS numbers on the TDM bus have different values. Is set. The data received from the terminal line A is transmitted from the T
The output is sent to the TS on the DM transmission bus E. At this time, the time switch circuit 4 determines the TS on the TDM reception bus F assigned to the line interface circuit 3 according to the specified TS replacement information d from the control circuit 5. Replace the data. The line interface circuit 3 takes in data from the specified TS on the receiving bus F and sends it out to the uplink line C-2 of the trunk line C. Conversely, the data received from the downlink C-1 of the trunk line C is output from the line interface circuit 3 to the specified TS on the TDM transmission bus E. At this time, the time switch circuit 4 switches the specified TS. The data is replaced with the TS on the TDM reception bus F allocated to the channel interface circuit 1 according to the information d. The channel interface circuit 1 receives the specified T
The multiplexed data is fetched from the TS on the DM reception bus F and transmitted to the up line A-1 of the terminal line A.

[0017] Then, in the case of a line using bypass means,
Next , the data flow in this case will be described. When serial data from the downlink B-1 of the trunk B is bypassed to the uplink C-2 of the trunk C, the line interface circuit 2 terminating the trunk B is set with normal TS allocation information. In the line interface circuit 3 that terminates the trunk line C, the TS allocation information for bypass is set, and the same value is set for the TS number on the TDM bus. The received data from the downlink B-1 of the trunk line B is output from the line interface circuit 2 to the designated TS on the TDM transmission bus E. At this time, the line interface circuit 3 switches the time switch circuit 4 at the same timing. The multiplexed data is fetched directly from the TDM transmission bus E without passing through, and transmitted to the uplink line C-2 of the trunk line C. Conversely, the data received from the downlink C-1 of the trunk line C is transmitted to the T
The multiplexed data is output to the TS on the DM receiving bus F and multiplexed data is directly fetched from the TDM receiving bus F without passing through the time switch circuit 4 at the same timing and transmitted to the upstream line B-2 of the relay line B. I do. That is, the signal exchange operation from the trunk line B to the trunk line C is performed by only one TS on the TDM transmission bus E, and the signal exchange operation from the trunk line C to the trunk line B is performed on the TDM reception bus F. Since the operation is performed by only one TS, the time switch circuit 4 does not need to perform the switching operation.

FIG. 4 shows an example of TS allocation on the TDM transmission / reception bus in this embodiment. Each of the TDM transmission bus E and the TDM reception bus F has one byte 8
When a bit-parallel high-speed transmission path has a code rate of, for example, 32 Mbps, TS is set to a frame pulse position of 125 μs per frame as TS number 0, and TS numbers 0 to 5
Up to 11 are given. Assuming that 16 Mbps handles bypass data as a configuration of the time division multiplexer, the TS numbers 256 to 511 are used as bypass TSs, and the TS numbers are sent from the control circuit 5 to the line interface circuits 2 and 3. To be specified for each. The time switch circuit 4 controls the TS of the multiplexed data between the channel interface circuit 1 and the line interface circuits 2 and 3 only for the TS numbers 0 to 255.
Are replaced, and the TS replacement operation is not performed for the TSs with the TS numbers 256 and thereafter.

[0019]

As described above, according to the present invention, the control circuit sets the TS allocation information having the same number as the TS number set in the other interface circuit in one of the interface circuits to be bypassed. , The data received from one line interface circuit can be directly transmitted from the other interface circuit without passing through the time switch circuit. Delay time is reduced. Similarly, the TS that the time switch circuit uses on the time division multiplexing transmission / reception bus
Since the number can be reduced by the number of bypass TSs as compared with a conventional multiplexing device that passes through a time switch circuit, a circuit size time switch circuit that terminates a TS smaller than the multiplexing capacity of the time division multiplexing transmission / reception bus. Can be configured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a time slot allocation method of a time division multiplexing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an interface circuit of the embodiment.

FIG. 3 is a timing chart for explaining a time slot allocating method of the time division multiplexer of the embodiment.

FIG. 4 is a diagram showing an example of TS allocation on a time division multiplex bus according to the embodiment.

FIG. 5 is a block diagram showing a time slot allocation method of a conventional time division multiplexing device.

FIG. 6 is a block diagram showing a conventional interface circuit.

FIG. 7 is a block diagram for explaining a time slot allocation method of a conventional time division multiplexing device.

[Explanation of symbols]

 Reference Signs List 1 channel interface circuit 2, 3 line interface circuit 4 time switch circuit 5 control circuit 10 multiplexing circuit 11 transmission selector 12 input / output gate 13 input / output gate 14 reception selector 15 demultiplexing circuit a to c TS allocation information d TS replacement information eh Control signal i Internal reference clock & frame pulse

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-18140 (JP, A) JP-A-1-256243 (JP, A) JP-A-7-46209 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04J 3/00-3/26

Claims (3)

(57) [Claims] A plurality of multiplexing means for each transmission line for multiplexing downlink line data from a transmission line into a designated time slot of a time division multiplex transmission bus;
A time slot switching means for replacing data of a designated time slot of the first multiplexed data multiplexed on the time division multiplex transmission bus with a designated time slot of the time division multiplex reception bus; A plurality of demultiplexing means for demultiplexing the data of the designated time slot from the second multiplexed data on the bus and transmitting the data in the upstream direction corresponding to each of the plurality of transmission lines; In the slot allocation method, when the downlink line data from a certain transmission line is bypass-transmitted to another transmission line in the upward direction, a time slot on the time division multiplex transmission bus and the time division multiplex reception bus The time slots are switched only on the time division multiplexing transmission bus or the time division multiplexing reception bus without exchanging the above time slots. Time slotted allocation method when division multiplexer, characterized in that it comprises means for scan. 2. A time slot multiplexing method for a time division multiplexing apparatus for multiplexing / demultiplexing downlink data from a transmission line and transferring the multiplexed data to an uplink line of another line. Normal means for exchanging time slots between the uplink and the line data is used.
In the case of a line to be used , downlink line data of the transmission line is multiplexed into a first time slot on a time division multiplexing transmission bus specified by first time slot allocation information, and the time division multiplexing is performed. The downlink data multiplexed on the transmission bus is designated by time slot exchange information, and the time slot
The downlink data exchanged from the first time slot on the transmission bus to the second time slot on the time-division multiplex reception bus is demultiplexed in accordance with the second time slot allocation information, and the transmission line of another line is transmitted. In the case of a line using bypass means for not transferring the time slots of the downlink line data and the uplink line data, and transferring the downlink line data and the uplink line data, with multiplexing in the third time slot on division multiplexing receiving bus when the specified downlink channel data in the third time slot with allocation information, other multiplexed in the time division multiplexed bus A line for multiplexing and demultiplexing downstream line data of a line transmission line in accordance with the third time slot allocation information and bypass-transferring the transmission line upward. And a plurality of line interface means having: the downlink line data of the designated time slot on the time division multiplex transmission bus according to the time slot exchange information; and the designated time slot on the time division multiplex reception bus. Means for exchanging time slot information; outputting the first, second, and third time slot allocation information and supplying the information to each of the plurality of line interface means, and outputting the time slot exchange information, Control means for supplying to the time slot exchanging means; and a time slot allocating method for the time division multiplexing apparatus. 3. The line interface means comprises a normal means for exchanging time slots between downlink data and uplink data of the transmission line.
In the case of a line to be used, the downlink line data to be multiplexed to the first time slot on the time division multiplex transmission bus is transmitted to the time division multiplex transmission bus, and the downlink line data is A bypass for not exchanging the time slot with the uplink line data
Means for transmitting the downlink line data to be multiplexed to the first time slot on the time division multiplex transmission bus to the time division multiplex reception bus in the case of a circuit using the means; In the case of a line using a normal means for performing a time slot exchange between line data in the downlink direction and line data in the uplink direction of the transmission line, in the case of a line using the uplink, the downlink for the demultiplexing is transferred to the uplink. Directional circuit data from the time-division multiplex receiving bus,
And not to exchange the time slots between the downlink line data and the uplink line data .
In the case of a line using a bypass unit, there is provided a second selection unit that takes in the downstream line data for demultiplexing to be transferred in the upstream direction from the time division multiplex transmission bus. 3. A time slot allocating method for a time-division multiplexing device according to claim 2.