JP3062361B2 - Compression device and expansion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compression device and a decompression device , and more particularly, to a TDMA (Time Division Multiplex).
iple Access: a compression device for transmitting a continuous digital signal in the TDD communication system
And a stretching device .

[0002]

2. Description of the Related Art Conventional compression and expansion devices are described below.
A description will be given based on FIGS. In the figure, 21,
23 is a serial input-parallel output 160-bit shift register, 22 and 24 are parallel input-serial output 160-bit shift registers, the input terminal is a continuous digital signal input terminal, and the output terminal is a continuous input signal at the input terminal. The burst signal output terminal and input terminal of the compressed signal are the input terminal of the clock of continuous digital signal speed, the input terminal is the input terminal of the clock of burst signal speed, the input terminal is the input terminal of the burst signal, and the output terminal is The output terminal of the continuous digital signal obtained by expanding the burst signal input at the input terminal, the input terminal is the input terminal of the clock of the burst signal speed, and the input terminal is the input terminal of the clock of the continuous digital signal speed.

A continuous digital signal input from an input terminal is output in parallel to a lower-stage shift register 22 every time 160 bits are stored in the shift register 21, and is output from the shift register 22 by a high-speed clock at a transmission slot timing. And serially output as a burst signal. The 160-bit burst signal input from the input terminal at the timing of the receiving slot is stored in the shift register 23, then output in parallel to the lower shift register 24, and output from the shift register 24 at a clock having a continuous digital signal speed. , And are serially output as a continuous signal.

[0004]

As described above, according to the conventional compression device and decompression device , the shift register 22 and the shift register 23 do not operate except when a burst signal is output or input. However, there is a disadvantage that the circuit scale is unnecessarily large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and switches a clock for operating a shift register, handles a continuous digital signal and a burst signal with a common shift register, and reduces the circuit scale. It is an object of the present invention to provide a compression device and an expansion device .

[0006]

To achieve the above object, the present invention provides: (1) a method of converting a continuous digital signal into a burst signal;
A continuous digitizer,
Shift register that shifts the clock signal with a low-speed clock
A low-speed clock or high-speed
A second shift register that shifts at a high speed clock;
The output of the first or second shift register is set to low speed or high speed.
No. that is shifted by a clock and output as a burst signal
3 shift register, and during the output period of the burst signal,
Supply high-speed clock to second and third shift registers
And outputs the output of the second shift register to the
3 during the other period.
Supply low-speed clock to second and third shift registers
And the output of the first shift register is changed to the third shift register.
Providing compression control means for supplying to the shift register
Or (2) the burst signal is continuously digitized.
A decompression device that outputs the berth signal
A fourth shifter that shifts the clock signal with a low-speed or high-speed clock
Shift register and the output of the fourth shift register at low speed.
Shift by clock and output as continuous digital signal
A fifth shift register, and a fourth shift register.
Data output is shifted by a low-speed or high-speed clock to
A sixth shift register for outputting as a digital signal,
During the input period of the burst signal, the fourth and sixth shifts are performed.
A high-speed clock is supplied to the register and the fourth
The output of the shift register is supplied to the sixth shift register.
During the other periods, the fourth and sixth shift registers
A low-speed clock is supplied to the
The output of the register is supplied to the fifth shift register.
Extension control means is provided .

[0007]

The continuous digital signal is divided into a burst signal of 160 bits at a time from the beginning of one transmission slot to the beginning of the next transmission slot. The received 160-bit burst signal is extended from the end of the reception slot to the end of the next reception slot, and becomes a continuous digital signal. The compression / expansion is performed by switching the clock input to the shift register.

[0008]

Embodiments will be described below with reference to the drawings. First, the TDMA-TDD communication method will be described with reference to FIG. One frame is composed of a total of eight slots, four transmission slots (T1 to T4) and four reception slots (R1 to R4). A continuous signal is compressed in a cycle in which transmission slots of the same number are repeated, and bursts are generated. The burst signal transmitted in the same manner and received in the reception slot of the same number is expanded in the cycle and becomes a continuous signal.
Here, a description will be given assuming that the number of bits of a continuous signal transmitted in one slot is 160 bits.

In the TDMA system, an exclusive channel (communication path: time slot) is basically set by a time-division multiplexing method between both communicating nodes, and a data signal is transmitted on the channel until the communication is completed. This is a method for transmitting and receiving data. This method is a circuit switching method in which a channel is set one-to-one between nodes of a communication partner.

FIGS. 1A and 1B show the compression according to the present invention.
FIG. 2 is a configuration diagram for explaining an embodiment of the device and the decompression device . FIG. 2 is a timing chart of signals of respective parts in FIG. In the figure, 1, 2, 5, and 6 are shift registers of 20 bits, 3 and 4 are shift registers of 140 bits, a is an input terminal of a continuous digital signal, and b is a burst signal obtained by compressing a continuous signal input at a. C, an input terminal for a clock having a continuous digital signal speed, d is an input terminal for a clock having a burst signal speed, and e is a control signal which is high only during a used transmission slot (tentatively T1). The input terminal, f is the input terminal of the burst signal, g is the output terminal of the continuous digital signal obtained by expanding the burst signal input by e, h is the input terminal of the clock of the continuous digital signal speed, and i is the input terminal of the clock of the burst signal speed. Input terminal,
j is an input terminal of a control signal which becomes High only during a used receiving slot (tentatively R1).

In FIG. 2, SW1 is a control signal input to e of FIG. 1, a continuous digital signal is a signal input to a of FIG. 1, a burst signal is a signal output from FIG. The signal input to c of FIG. 1 and the high-speed clock are the signals input to d of FIG.
1 is a control signal input to j in FIG. 1, a burst signal is a signal input to f in FIG. 1, and a continuous digital signal is
The low-speed clock signal output from g of FIG.
And the high-speed clock is the signal input to i in FIG.

First, a compression operation for outputting a continuous digital signal as a burst signal will be described with reference to FIG. It is assumed that the continuous digital signal is divided into a burst signal of 160 bits at a time from the beginning of a certain transmission slot to the beginning of the next transmission slot. While SW1 is High, 20 bits of the continuous signal are stored in the shift register 1. Further, the shift register 2 and the shift register 3 are connected, a high-speed clock is input, and a burst signal is transmitted. SW
When 1 becomes low, the shift register 1 and the shift register 3 are connected.
0-bit operation is performed, and the storing operation is also performed in the shift register 2. When SW1 goes high again, the contents of the signals of the shift register 1 and the shift register 2 at that moment are the same, so that the shift register 2 and the shift register 3 are connected and burst transmission is performed. There is no problem to go. By repeating the above operation, the continuous digital signal is compressed into a burst signal.

Next, the expansion operation for outputting a burst signal as a continuous digital signal will be described below with reference to FIG. It is assumed that the received 160-bit burst signal is extended from the end of the reception slot to the end of the next reception slot to become a continuous digital signal. S
While W2 is High, the shift register 4 and the shift register 6 are connected, and a high-speed clock is input.
A burst signal is received. When SW2 becomes low, a low-speed clock is input to the shift register 4 and the shift register 6, and the expanded 140-bit signal starts to be output from the output terminal g. The shift register 5 has
Since the low-speed clock continues to be input, SW2 switches again.
The content of the 20-bit signal of each of the shift register 5 and the shift register 6 at the time when the signal becomes High is the same. When SW2 becomes High, the output to the output terminal g is performed from the shift register 5, so that the remaining 20-bit signal is output without any problem, and the burst signal is received using the shift register 4 and the shift register 6. Has been done. By repeating the above operation, a continuous digital signal is expanded from a burst signal.

[0014]

Since the present invention is configured as described above, it has the following effects. That is, by switching the clock for operating the shift register, the continuous digital signal and the burst signal are handled by the common shift register, so that there is an advantage that the circuit scale can be reduced to almost half of the conventional circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a compression device and an expansion device according to the present invention.

FIG. 2 is a timing chart of signals of respective parts in FIG.

FIG. 3 is a configuration diagram of a TDMA-TDD communication system for explaining a compression device and a decompression device according to the present invention.

FIG. 4 is a view for explaining a conventional compression device and expansion device .

[Explanation of symbols]

1, 2, 5, 6 ... 20-bit shift register, 3, 4, ... 14
0-bit shift register, a: input terminal of continuous digital signal, b: output terminal of burst signal obtained by compressing the continuous signal input at a, c: input terminal of clock of continuous digital signal speed, d: burst signal speed , Input terminal of a control signal which becomes High only during the transmission slot (tentatively, T1) being used, f ...
An input terminal for a burst signal, an output terminal for a continuous digital signal obtained by expanding the burst signal input at g ... e, an input terminal for a clock at a continuous digital signal speed, an input terminal for a clock at a burst signal speed, and j ... An input terminal for a control signal that goes high only during the used receiving slot (tentatively R1).

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04J 3/00 H04Q 7/38 H04L 13/08 H04L 7/00

Claims (2)

(57) [Claims] A continuous digital signal is a burst signal.
The continuous digital signal is shifted by a low-speed clock.
A first shift register, and a low-speed clock or a high-speed clock for the continuous digital signal.
A second shift register that shifts at high speed and an output of the first or second shift register at low speed or high speed.
Output as a burst signal after shifting with the high speed clock
A third shift register and the second and third shift registers during a burst signal output period.
A high-speed clock is supplied to the register, and the second
The output of the shift register is supplied to the third shift register.
During the other period, the second and third shift registers
A low-speed clock is supplied to the first shifter and the first shift
The output of the register is supplied to the third shift register.
And a compression control means . (2) The burst signal is a continuous digital signal.
Output decompression device, Shifting the burst signal with a low-speed or high-speed clock
A fourth shift register, The output of the fourth shift register is shifted by a low-speed clock.
5th shift to output as a continuous digital signal
Registers and The output of the fourth shift register is clocked at low speed or high speed.
Output as a continuous digital signal after shifting
6 shift registers; During the input period of the burst signal, the fourth and sixth shifts are performed.
A high-speed clock is supplied to the register and the fourth
The output of the shift register is supplied to the sixth shift register.
During the other periods, the fourth and sixth shift registers
A low-speed clock is supplied to the
The output of the register is supplied to the fifth shift register.
An expansion device, comprising: an expansion control unit.