JPH04129341A - Multiplex signal selection separation circuit - Google Patents

Abstract

PURPOSE:To select and separate even a multiplex signal of any channel number by varying a clock generation period of a clock generating circuit and a count period of a latch pulse generating circuit in response to number of channels of the multiplex signal. CONSTITUTION:The multiplex signal selection separation circuit starts counting with a latch pulse synchronously with a head of a period of a multiplex signal outputted from a clock generating circuit and makes counting synchronously with one bit period of the multiplex signal. A latch circuit latches one channel signal from an inputted multiplex signal by using a carrier signal from a latch pulse generating circuit counting a channel number being an output from a channel designation circuit. A clock generating period of the clock generating circuit and a count period of the latch pulse generating circuit are varied in response to the channel number of the multiplex signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a multi-channel PCM satellite music broadcasting receiver that extracts a signal for one channel selected from a multiplexed signal obtained by time-division multiplexing multiple channels. The present invention relates to a multiplex signal selection/separation circuit in, for example, a multi-signal selection/separation circuit.

Conventional technology For example, P in multi-channel PCM satellite music broadcasting.
CM (Pulse Code Modulation
) In a receiver that receives multiplexed signals, in order to extract the signal of one channel selected from the multiplexed signal,
It has been proposed to incorporate a multiplexed signal selection/separation circuit having the configuration shown in the figure.

This multiplex signal selection/separation circuit is a circuit for selectively separating a 12-channel multiplex signal in the case of audio broadcasting for CATV distribution. is latched.

The multiplexed signal for one period latched by the 12-bit shift register 1 is sent to the 12-to-1 selector 2 as a 12-bit parallel signal, and the one selected by the channel selection signal input separately to the 12-to-1 selector 2 is sent to the 12-to-1 selector 2 as a 12-bit parallel signal. The signals of the two channels are outputted from the 12-to-1 selector 2, and the signals are taken into the latch circuit 3 operated by the data latch clock synchronized with the period of the multiplexed signal, and outputted from the latch circuit 3 as data.

Problems to be Solved by the Invention However, in the case of the above-mentioned conventional multiplex signal selection/separation circuit,
A shift register 1 having the number of bits equal to the number of channels of the multiplexed signal N is prepared, and a selector 2 for selecting one channel from the number N of channels is N.
A pair-to-one selector is required, and there is a problem that the circuit scale increases as the number of channels N increases.

In addition, when receiving several types of multiplexed signals with different numbers of channels N, multiple types of multiplexed signal separation circuits having shift registers 1 and selectors 2 corresponding to the number of channels N of each multiplexed signal must be prepared. , it also has the problem of lacking versatility.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a highly versatile multiplexed signal selection/separation circuit that has a small circuit scale, low power consumption, and can be applied to multiplexed signals with any number of channels.

Means for Solving the Problems The present invention provides a latch circuit that receives a multiplexed signal obtained by time-division multiplexing multiple channels and holds the signal for one channel at the input timing of a separately input latch pulse, and the multiplexed signal. a clock generation circuit that outputs a clock at the timing when the first channel signal of one period of the serial signal is input to the latch circuit; and channel number information of the signal to be separated from the multiplexed signal. a channel designation circuit that outputs one of the multiplexed signals;
Consists of a counter that counts in synchronization with the bit cycle.
A latch pulse that takes the number of channels, which is output information from the channel designation circuit, as a preset value, starts counting by the clock from the clock generation circuit, and outputs a carrier signal as a latch pulse to the latch circuit when the preset value is counted. 1 is a multiplexed signal selection/separation circuit characterized by comprising a generation circuit;

Effect According to the present invention, by changing the clock generation period of the clock generation circuit and the count period of the latch pulse generation circuit according to the number of channels of multiplexed signals, any kind of operation can be performed without changing the circuit configuration. Selective separation of signals can also be performed for multiplexed signals with a number of channels.

Embodiment FIG. 1 is a block diagram showing the basic configuration of a multiplexed signal selection/separation circuit which is an embodiment of the present invention.

The first latch circuit 4 is a 1-bit latch circuit for sequentially latching each bit of the input multiplexed signal, that is, the signal for each channel of the multiplexed signal.
A latch operation is performed at the timing of a high-order multiplex clock synchronized with the bit period.

A second latch circuit 5 is connected to the next stage of the latch circuit 4 for latching the signal of one selected channel among the signals output from the latch circuit 4.

This latch circuit 5 performs a latch operation at the timing of a latch pulse output from the latch pulse generating circuit 7.

Furthermore, a third latch circuit 6 is connected to the next stage of the second latch circuit 5 for latching the signal output from the latch circuit 5 at a different timing. This latch circuit 6 performs a latch operation at the timing of the normalized clock output from the control circuit 8. The normalized clock is the first one of the serial signals for one period of the multiplexed signal.
The signal of the channel is output at the timing when it is input to the latch circuit 5.

The latch pulse generation circuit 7 consists of, for example, a 5-bit down output, has a function of counting in synchronization with the 1-bit period of the multiplexed signal, and has a preset value set according to the channel selection signal given from the control circuit 8. The signal obtained by inverting the normalized clock described above by the inverter 9 is received as the load signal L○AD, and the load signal LOA
At the input timing of D, it starts counting down from the preset value to 0, and when the count value reaches 0, it outputs a carrier signal. This carrier signal is applied to the latch circuit 5 as a latch pulse.

The channel selection signal given from the control circuit 8 to the latch pulse generation circuit 7 is data on the number of channels N of the signal to be separated from the multiplexed signal, and the number N of channels is set as a preset value in the latch pulse generation circuit 7. be done.

FIG. 2 is a timing chart showing the operation of the multiplexed signal selection/separation circuit, in which FIG. 2(1) shows the multiplexed signal, FIG. 2(2) shows the latch pulse, and FIG. 2(3) shows the latch pulse. The output of the second latch circuit 5 is shown, FIG. 2 (4) shows the normalized clock, and FIG. 2 (5) shows the output of the third latch circuit 6.

In addition, in FIG. 2 (1), 1', 2' to 61
represents the signals of channels 1, 2 to 6 in the first period of the multiplexed signal, 12, 22 . ~62 are 1, 2 . . . in the second period of the multiplexed signal. ~6 channel signals, lj, 2
ff, ~63 are 1, 2 in the third period of the multiplexed signal
．． ~6 channels of signals are shown, respectively.

Next, the operation of the multiplexed signal selection and separation circuit will be explained with reference to FIG.

Assuming that one channel signal selected from a multiplexed signal of a multichannel PCM satellite music broadcast for personal distribution is to be selectively separated, the number of channels N of the multiplexed signal in this case is six. Further, the transmission rate of the low-order multiplexed signal at this time, that is, the transmission rate of the PCM signal for one channel in the multiplexed signal, is 2.048 Mb/s. Therefore, the transmission speed of 6 channels of multiplexed signals is 6X2.048Mb/5=1
It is 2.288 Mb/s.

In accordance with this transmission speed, the frequency of the high-order multiplexed clock given from the control circuit 8 to the first latch circuit 4 is 12.
The frequency is set to 288MHz. Therefore, the first latch circuit 4 sequentially latches each bit of the input multiplexed signal, that is, the signal of each channel, and each latched signal is sequentially input to the second latch circuit 5.

When the multiplexed signal selection and separation circuit selectively separates three channels of signals from the multiplexed signal, the control circuit 8 sends three channel selection signals to the latch pulse generation circuit 7.
Data (00011) specifying the channel is sent,
This data is set in the latch pulse generation circuit 7 as a preset value.

Furthermore, the operating speed of the latch pulse generating circuit 7 is set so that the counting operation is performed using a clock of 12.288 MHz in accordance with the transmission speed of the multiplexed signal.

Furthermore, the normalized clock output from the control circuit 8 is
As shown in FIG. 2 (4), the first signals 1', 12, 13 . is set to rise at the timing when the signal is input to the second latch circuit 5.

Therefore, at the timing when the first channel signal 11 of the multiplexed signal of the first period is input to the latch circuit 5, a signal obtained by inverting the normalized clock is input to the latch pulse generation circuit 7 as the load signal LOAD, and from this point on, The latch pulse generation circuit 7 starts counting down.

When the latch pulse generation circuit 7 counts down at t to set the preset value to 0, that is, when it counts down by 3 clocks, a carrier signal is output from the latch pulse generation circuit 7, and this carrier signal is shown in FIG.
2) is applied to the second latch circuit 5 as a latch pulse shown in FIG. This timing is the timing at which the three-channel signal 3I in the first cycle of the multiplexed signal is input to the latch circuit 5, and at this time, the three-channel signal 31 is latched into the latch circuit 5.

Similarly, the 3-channel signal 32 is transmitted in the second period of the multiplexed signal, and the 3-channel signal 32 is transmitted in the third period of the multiplexed signal.
3 are sequentially latched by the opening circuit 5.

Further, the signals 3', 32.3', . . . of each three channels outputted from the latch circuit 5 are sequentially latched by the next-stage up-chip circuit 6 at the timing of the rising edge of the normalized clock. The signal that was set is shown in Figure 2 (5).
The selected and separated data are sequentially output as shown in FIG. The output timing of the signal output from the second latch circuit 5 differs depending on the selected channel, but the third latch circuit 6 always latches at the timing when the signal of one channel appears at the beginning of the period of the multiplexed signal. Therefore, no matter which channel is selected as the channel to be separated, the output timing of the separated data from the latch circuit 6 is constant.

By the way, when the number of channels N of a multiplexed signal is 12, the transmission speed of the multiplexed signal is 12X2.04.8Mb/5=2
4.576 Mb/s, which is twice as much as in the previous case, so when attempting to selectively separate this multiplexed signal with the multiplexed signal selection/separation circuit, the latch operation speed of the latch circuit 4 and the Sochi pulse generation circuit 7 are required. This can be achieved simply by doubling the counting operation speed of , and the channel to be selected can be easily changed by simply variably setting the channel selection signal output from the control circuit 8.

Note that here, since the latch pulse generation circuit 7 is composed of a 5-bit counter, the preset value is 1 to 2'.
It can be set up to =32. In other words, it is possible to selectively separate multiplexed signals having up to 32 channels.

Effects of the Invention As described above, according to the multiplex signal selection/separation circuit of the present invention, counting is started with a latch pulse synchronized with the beginning of the cycle of the multiplex signal output from the clock generation circuit, and one bit period of the multiplex signal is The carrier signal from the latch pulse generation circuit, which counts the number of channels output from the channel designation circuit, is used as a latch pulse, and the latch circuit uses the signal of one channel from the input multiplexed signal as a latch pulse. Since it is configured to latch, it is possible to change the clock generation period of the clock generation circuit and the count period of the latch pulse generation circuit according to the number of channels of multiplexed signals, without changing the circuit configuration. Selective separation of signals can be performed even for multiplexed signals with such a number of channels.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a multiplexed signal selection/separation circuit which is an embodiment of the present invention, FIG. 2 is a timing chart showing its operation, and FIG. 3 is the basics of a conventional multiplexed signal selection/separation circuit. 1 is a block diagram showing the configuration of the system. 5.6...Latch circuit, 7...Latch pulse generation circuit, 8...Control circuit Agent Patent attorney Keiichi Saikyo Team Coordination Diagram

Claims (1)

[Scope of Claims] A latch circuit that receives a multiplexed signal obtained by time-division multiplexing multiple channels and holds the signal for one channel at the input timing of a separately input latch pulse; a clock generation circuit that outputs a clock at the timing when the first channel signal of the serial signal is input to the latch circuit; and a channel designation circuit that outputs channel number information of the signal to be separated from the multiplexed signal. and a counter that counts in synchronization with the 1-bit period of the multiplexed signal, uses the number of channels, which is the output information from the channel designation circuit, as a preset value, starts counting by the clock from the clock generation circuit, and performs a preset counter. A multiplexed signal selection and separation circuit comprising: a latch pulse generation circuit that outputs a carrier signal as a latch pulse to the latch circuit after counting the value.