SU1354426A1 - Apparatus for separating digital channels - Google Patents

Abstract

DEVICE FOR THE DESTINY OF DIGITAL CHANNELS

The invention relates to telecommunications. The purpose of the invention is to increase the t f the number of channels to be allocated. The device contains receivers 1,3 and 5, and transmitters 2, 4 and 6 of the first, second and third lines, keys 7–9, memory blocks 10–12, transducers 13 and 14 of the cycle phase, control blocks 15 and 16, respectively. . The use of this device in the local network nodes allows, without any restrictions on the number of digital channels to be allocated, it is most efficient to distribute these channels in the network lines on the specified direct channels between its points. 1 Ill. 9 (L SA :) SP

Description

The invention relates to telecommunications and can be used in digital communication networks with a linear or tree structure for allocating digital channels in nodes.

The purpose of the invention is to increase the number of allocated channels.

The drawing shows a structural electrical circuit for allocating digital channels.

The device comprises a receiver 1 and transmitter 2 of the first line, receiver 3 and transmitter 4 of the second line, receiver 5 and transmitter 6 of the third line, first 7, second 8 and third 9 keys, first 10, second 11 and third 12 memory blocks, first 13 and the second 14 cycle phase converters, the first 15 and second 16 control units.

The digital channel allocation device operates in the following manner.

In receivers 1,3 and 5 of each line, group digital signals (GCC) are converted from a linear code to a binary code available for digital processing. The received and second and third lines of the GCC are fed to converters 13 and 14 of the loop phase, which convert the phases of the GDS of the indicated lines respectively, in the first line GSS phase, which is necessary for the synchronous combination of channel digital signals (MCC) in keys 7–9, Next, the MCC components from each line of the MCC are cyclically recorded and acyclically read from blocks 10–12 of memory. From the outputs of these memory blocks, the MCC is fed to the inputs of the corresponding keys, which are synchronously combined into the outgoing GCCs. The latter in the transmitters with a kalod l. Lines are supplemented with cyclic and superframe synchronization signals and are converted from binary code to a linear code. Control blocks 15 and 16 generate address and read signals for memory blocks 10–12, as well as switching signals from one of the inputs of keys 7–9 to their outputs. To implement three direct channels, it is necessary that the MCC received from

all lines in CI were recorded in

corresponding memory blocks in those

same 1W;, 1 a. read and transmit through the keys 7-9 to the transmitters 2,4 and 6 of each line in KHj. Conversely,

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MCCs received from all lines in CIs are recorded in memory blocks in the same CIs, and are read and transmitted via keys to the transmitters of each line in KMj.

Thus, the device for allocating digital channels ensures the allocation of any number of digital channels not exceeding n from the first and second lines to the third line.

The use of the device for allocating digital channels in the nodes of a local network allows, without limitation, the number of dedicated digital channels and most efficiently distribute these links in the network along the specified direct channels between its points.

Claims (1)

Invention Formula A digital channel allocation device containing a receiver and a transmitter in each of the three lines, the first, second and third keys, the first, second and third memory blocks, the first and second cycle phase converters, the first and second control blocks, the first receiver output line is connected to the input of the first memory block, the output of which is connected to the first input of the second key, the output of which is connected to the input of the third line transmitter, and the second input of the second key is connected to the outputs of the second memory block, the third key output is connected to the input of sensor- first line and the second input of the third switch is connected to the output of the third memory unit, an input coupled to. the output of the second phase converter of the cycle, the input of which is connected to the output of the third line receiver, the output of the first key is connected to the input of the second line transmitter, the outputs of the first control unit are connected to the control inputs of the first and second memory blocks, the first and second keys, the second the control unit is connected to the control inputs of the third key and the third memory block, which is characterized by the fact that, in order to increase the number of channels to be allocated, the output of the first memory block is connected to the first input of the first key, the second in the course of which is connected to the output of the third memory block, the output 31354426 4 The receiver of the second line is connected to the input of the second memory unit, the output to the input, the first phase converter of which is connected to the second input of the cycle, the output of which is connected to the third key. Compiled by S.E. n Editor M.Blanar Tehred M.Hodanich Proofreader G. Reshetnik Order 5715/55 Circulation 636 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4