JP2978614B2 - Synchronous multiplex switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous multiplex switching circuit for synchronously multiplexing multiple asynchronous data signals in a communication system.

[0002]

2. Description of the Related Art Conventionally, in order to synchronously multiplex and exchange asynchronous data signals in a small-scale circuit, as shown in FIG. 10, an input data signal is written into an elastic store memory with each clock, and the input data signal is Are read out with a clock of a multiplexing circuit, and are synchronized and octet-multiplexed to a time division multiplexing (TDM) signal. Further, the time division multiplexed signal is supplied to a T single-stage switch, and the T single-stage switch realizes digital exchange by exchanging time slots on the TDM signal in octet units.
However, in this method, since the call memory and the control memory must be accessed periodically, the number of exchangeable channels is limited to about 1000, being limited by the cycle time for accessing.

Therefore, in order to handle a larger number of channels using a T switch that exchanges both input and output with TDM signals, as shown in FIG. 11, a T switch is used in combination with an S switch that exchanges a plurality of TDM signals. In a TST configuration, signals that are temporally exchanged in the switch are spatially exchanged by the S switch, and then exchanged by the T switch, and then demultiplexed. In some cases, a T-stage configuration in which T-switches are superposed in multiple stages as shown in FIG. 12 was used, but in each case, a complicated and large-scale circuit configuration had to be taken.

On the other hand, a pulse stuffing method has been used in order to avoid a slip which occurs when a plurality of asynchronous low-speed data signals are multiplex-converted into a time division multiplex (TDM) signal. The pulse stuffing method uses a line capable of transmitting a signal having a speed higher than the sum of all input data rates in a multiplexing circuit as shown in FIG. 13 and appropriately applies an extra code to a time-division signal sequence. To make each asynchronous data signal a synchronous relationship. That is, a non-information bit (stuff pulse) is inserted according to the difference between the asynchronous data signal and the clock frequency to be synchronized, thereby synchronizing the clock frequency. In this way, a plurality of asynchronous signals are synchronously multiplexed to prevent slippage on the receiving side.

[0005]

As described above, the conventional multiplex switching circuit has a problem that the circuit configuration must be complicated to handle a large number of channels.
In addition, in such a circuit, in order to prevent slippage using the conventional pulse stuffing method, it is necessary to add a non-information bit as necessary for each input channel and to determine whether the non-information bit is inserted. A function of adding a stuff control bit indicating the above is required. That is, it is necessary to insert a non-information bit at a predetermined digit position on a frame and arrange a stuff control signal for each frame to indicate the presence or absence of the non-information bit. There was a problem that a large-scale circuit had to be provided.

Accordingly, an object of the present invention is to provide a synchronous multiplex switching circuit for multi-channel asynchronous data which can realize digital switching of thousands of channels by a small-scale circuit.

It is still another object of the present invention to solve an error caused by a slip that occurs when time-division multiplexing of asynchronous data is performed by a simple method.

[0008]

A synchronous multiplex switching circuit according to the present invention receives a plurality of asynchronous data signals transmitted from a plurality of channels, respectively, synchronizes the plurality of asynchronous data signals, and time-division multiplexes the signals. In a synchronous multiplex switching circuit for multiplexing the time-division multiplexed signal and outputting the multiplexed signal as a plurality of time-division multiplexed signals, the circuit is connected to the plurality of channels on a one-to-one basis and transmitted from the plurality of channels. A plurality of gate means for receiving an asynchronous data signal and outputting a plurality of synchronous data signals in response to a control signal; and the asynchronous data connected to all of the plurality of gate means and sent to the plurality of gate means. Control means for storing an order for synchronously multiplexing signals, and transmitting a signal indicating the stored order to the plurality of gate means as the control signal; A data bus that is connected to all of the plurality of gate means and collectively outputs the plurality of synchronous data signals output from the plurality of gate means as a synchronous multiplexed data signal; and Demultiplexing means for receiving a synchronous multiplexed data signal, demultiplexing the synchronous multiplexed data signal, and outputting the demultiplexed signal as the time-division multiplexed signal, wherein the order stored in the control means is By exchanging, the synchronous data signals output from the plurality of gate means can be optionally multiplexed and exchanged.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a synchronous multiplex switching circuit according to one embodiment of the present invention. Signal lines 10-1 to 10
−n (n is a natural number) is connected to the address gate switch circuits 20-1 to 20-n, respectively. The address gate switch circuits 20-1 to 20-n are all connected to the gate switch control circuit 30.

Address gate switch circuits 20-1 and 20-2
0-n are S / P conversion circuits (series-parallel conversion circuits)
21-1 to 21-n and an elastic buffer 22-
1 to 22-n and gate switches 23-1 to 23-n.

The S / P conversion circuits 21-1 to 21-n are provided with input data signals DS1 to DSn supplied as serial signals.
Is converted to a j-bit parallel signal to be handled in the subsequent circuits. The signals converted into parallel signals in the S / P conversion circuits 21-1 to 21-n are sent to the elastic buffers 22-1 to 22-n via the data bus, respectively. The elastic buffers 22-1 to 22-n convert parallel signals supplied from the S / P conversion circuits 21-1 to 21-n into respective asynchronous signals in order to synchronize input signals that are asynchronous with each other as described later. It is stored temporarily at the clock cycle of the signal. The gate switches 23-1 to 23-n transfer signals stored in the elastic buffers 22-1 to 22-n to the data bus 4 in response to a gate switch control signal from the gate switch control circuit 30, as described later.
Supply 0.

The gate switch control circuit 30 controls the gate switches 23-1 to 23-3 to be opened at each clock timing.
The -n address number is supplied to the gate switches 23-1 to 23-n as a gate switch control signal. The gate switches 23-1 to 23-n input from the elastic buffers 22-1 to 22-n with the clock of the gate switch control signal in the order indicated by the gate switch control signal supplied from the gate switch control circuit 30. The data signals DS1 to DSn are read and sequentially supplied to the data bus 40.

That is, the input data signals DS1 to DSn
Are supplied to the data bus 40 in a time-division multiplexed form in synchronization with the clock of the gate switch control signal in the order indicated by the gate switch control signal. In other words, the asynchronous input data signals DS1 to DSn are changed to time-division multiplexed signals by sequentially reading out the input data signals DS1 to DSn with the clock of the gate switch control signal. Therefore, by changing the order of the address numbers of the gate switches 23-1 to 23-n indicated by the gate switch control signal at this time, time division multiplexing and exchange can be performed simultaneously.

The time division multiplexed signal supplied to the data bus 40 is sent to an inverse multiplexing circuit 50. In the demultiplexing circuit 50, the high-speed time-division multiplexed signal supplied from the data bus 40 is demultiplexed regularly in the order of input, and output as TDM output signals OS1 to OSm (m is a natural number) at the target speed.

Next, the principle of the present invention will be described in more detail with reference to FIG.

FIG. 2A is a diagram showing an example of the input data signals DS1 to DSn supplied to the synchronous multiplex switching circuit shown in FIG. 1. FIGS. 2B and 2C are diagrams respectively. FIG. 3 is a diagram showing an example of a gate switch control signal and a time division multiplexed signal supplied to a data bus 40.

As described above, the elastic buffer 2
The j-bit parallel signals stored in 2-1 to 22-n are
The data is supplied to the data bus 40 in the order specified by the gate switch control signal. That is, in FIG. 2B, the gate switch control signals are CH2, CHn. . . Since the order is as shown in CH1, the signal stored in the elastic buffer is the B2 of DS2 as shown in FIG.
0, Xn of DSn,. . . The data is supplied to the data bus 40 via the gate switches 23-1 to 23-n in the order of A0 of DS1.

FIG. 3 is a conceptual diagram showing the configuration of the gate switch control circuit 30.

The gate switch control circuit 30 includes a memory circuit 31, a data bus 32, and a decoder 33. The memory 31 stores the address numbers of the gate switches corresponding to the respective input data signals in the order in which the input data signals are multiplexed with the output TDM signal. FIG.
CH2, CHn. . . When multiplexing is performed in the order of CH1, the memory circuit 31 stores the respective gate switch numbers 2, n,. . . , 1 is stored.

The data stored in the memory 31 is scanned by a scanner (not shown) and the data bus 32
Is supplied to the decoder 33 via the. The decoder 33
The supplied signal is decoded and output as a gate switch control signal.

As a clock cycle for generating a timing for opening the gate switch, a clock cycle slightly higher than the clock cycle of any input data signal including an error is selected. As a result, when focusing on one input data signal, duplicate data in units of j bits may be time-division multiplexed (slip) over two timings, but no data loss occurs.

FIG. 4 is a diagram showing an embodiment in a case of coping with multi-channel switching using the synchronous multiplex switching circuit shown in FIG.

The number of data input to the synchronous multiplex switching circuit shown in FIG.
Access is limited by the cycle time. Therefore, by providing a plurality of gate switches in parallel in one address gate switch circuit as shown in FIG.
Signals can be exchanged between a plurality of TDM signals without using a switch. Therefore, by adopting the configuration shown in FIG. 4, more input data signals can be handled.

FIG. 5 is a diagram showing a first embodiment of a communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied, and a time chart for explaining the operation thereof.

In FIG. 5A, a transmitting terminal 61 and a receiving terminal 62 are terminals that perform synchronous transmission using one timing bit for every j bits handled in parallel in the synchronous multiplex switching circuit. . This timing bit pattern is a repetition of “1” and “0”. The receiving terminal 62 selects a j-bit unit time slot from the TDM signal supplied from the synchronous multiplex switching circuit. In this case, a time slot corresponding to a target one of the data supplied from the transmitting terminal 61 is selected.
Further, the data transmitted from the transmitting terminal 61 is reproduced by sequentially arranging the selected data.

If no error occurs in the synchronous multiplex switching circuit, the receiving terminal 62 receives normal data as shown in FIG. However, when a slip occurs in the synchronous multiplex switching circuit, exactly the same j-bit data is received twice as shown in FIG. That is, since the timing bits are "1", "1", "0", and "0", the occurrence of a slip can be detected by detecting these consecutive same timing bits. When the occurrence of the slip is detected, the error from the occurrence of the slip is removed by regenerating the data from the transmitting terminal 61 while ignoring the j-bit data received at that timing.

FIG. 6 is a diagram showing a second embodiment of the communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied, and a time chart for explaining the operation thereof.

In FIG. 6A, a transmitting terminal 61 and a receiving terminal 62 are terminals that perform synchronous transmission using one timing bit for every j bits handled in parallel in the synchronous multiplex switching circuit. . This timing bit pattern is a repetition of “1” and “0” as in the case of FIG. 5, but the synchronous multiplex switching circuit is connected to a separation circuit 63 for separating the TDM signal into time slots. The receiving terminal 62 receives the continuous signal of only the transmission data of the target transmitting terminal 61 which is the output of the separation circuit 63.

In this case, when the separation circuit 63 separates the output TDM signal from the synchronous multiplex switching circuit into time slot units, the timing bits "1", "1" or "0""0" for each time slot. , And ignores the j-bit data of the time slot to which the timing belongs, and transmits data to the receiving terminal 62. This eliminates errors due to slip.

FIGS. 7, 8 and 9 show another embodiment of the communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied. In this case, the transmitting terminal 64 and the receiving terminal 66 are terminals that perform asynchronous transmission, or even terminals that perform synchronous transmission, one bit for every j bits handled in parallel in the synchronous multiplex switching circuit. , "1" and "0" are not inserted. For this reason, the bit insertion circuit 6 for slip detection is provided before the synchronous multiplex switching circuit.
5 is inserted, and a slip detection bit of a repeating pattern of 1 bit “1” and “0” is inserted for every (j−1) bits of the input data signal.

Referring to FIG. 7, by detecting "1", "1" or "0" or "0" of the slip detection bit of the target signal in the TDM signal supplied from the synchronous multiplex switching circuit, duplicate data is detected. Is ignored and the data of the transmitting terminal 64 is reproduced. For this reason, an error due to slip can be removed.

In FIG. 8, FIG.
A separation circuit 63 similar to the embodiment shown in FIG.
Output TD from synchronous multiplex switching circuit in separation circuit 63
When separating the M signal into time slots, the slip detection bits “1” and “1” for each time slot are used.
Alternatively, “0” or “0” is detected, and the data is transmitted to the receiving terminal 66 ignoring the j-bit data of the time slot to which the timing belongs. This eliminates errors due to slip.

In the embodiment shown in FIG. 9, the separating circuit shown in FIG. 8 is further connected to the multiplexing circuit 67. The separating circuit 63 separates the output TDM signal from the synchronous multiplex switching circuit into time slots, and detects "1", "1" or "0""0" of the slip detection bit for each time slot. Further, the j-bit data of the time slot to which the timing belongs is ignored (j
-1) An error due to slip is removed by time division multiplexing again in bit units. The TDM signal from which the error has been removed is sent to the receiving terminal 66.

As an application field of the present invention, there is a baseband exchange mounted on a satellite.

[0036] The satellite-mounted baseband switch needs to exchange a large number of input signals with a small-scale circuit, and the synchronous multiplex switching circuit according to the present invention can satisfy this condition. In addition, by using the synchronous multiplex switching circuit according to the present invention as a baseband switch mounted on a satellite, it becomes possible to use an asynchronous SCPC signal for each earth station for the uplink and a TDM signal for multiplexing a large number of signals for the downlink. Therefore, a system suitable for providing services to a moving earth station or a very small earth station can be realized. That is,
It can be used as a satellite switch for mobile satellite communication, personal satellite communication, and the like.

[0037]

As described above, according to the present invention,
Since synchronous multiplexing and exchange can be performed at the same time,
This has the effect that synchronous multiplex exchange of asynchronous data signals can be realized with a small-scale circuit.

Further, according to the present invention, there is an effect that it is possible to cope with an increase in the number of asynchronous data signals to be synchronously multiplexed and exchanged without adding an extra circuit by adopting a parallel configuration.

Further, according to the present invention, there is an effect that an error due to a slip which occurs when multiplex conversion of asynchronous data can be removed by a simple method.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a synchronous multiplex switching circuit according to the present invention.

FIG. 2 is a diagram showing an example of an input data signal, a gate switch control signal, and a time division multiplex signal supplied to a data bus, which are supplied to the synchronous multiplex switching circuit shown in FIG.

FIG. 3 is a conceptual diagram showing a configuration of a gate switch control circuit 30.

FIG. 4 is a diagram showing an embodiment in a case of coping with multi-channel switching using the synchronous multiplex switching circuit shown in FIG. 1;

FIG. 5 is a diagram showing a first embodiment of a communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied, and a time chart for explaining the operation thereof;

FIG. 6 is a diagram showing a second embodiment of the communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied, and a time chart for explaining the operation thereof;

FIG. 7 is a diagram showing another embodiment of the communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied.

8 is a diagram showing another embodiment of the communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied.

FIG. 9 is a diagram showing another embodiment of the communication system to which the synchronous multiplex switching circuit shown in FIG. 1 is applied.

FIG. 10 is a block diagram showing a configuration of a conventional synchronous multiplex switching circuit.

FIG. 11 is a block diagram showing a configuration of a conventional TST system.

FIG. 12 is a block diagram showing a configuration of a conventional T multistage system.

FIG. 13 is a diagram for explaining a conventional pulse stuffing method.

[Explanation of symbols]

 10-1 to 10-n Signal line 20-1 to 20-n Address gate switch circuit 21-1 to 21-n S / P conversion circuit 22-1 to 22-n Elastic buffer 23-1 to 23-n Gate Switch 30 gate switch control circuit 31 memory 33 decoder 40 data bus 50 demultiplexing circuit

Continuation of the front page (72) Inventor Minoru Endo 2-5-1-5 Iwamotocho, Chiyoda-ku, Tokyo Inside the National Institute of Space and Communications Technology (56) References JP-A-63-87832 (JP, A) JP-A-Hei 2-58940 (JP, A) JP-A-64-82798 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04J 3/00-3/26 H04Q 11/00

Claims (2)

(57) [Claims] 1. A method for receiving a plurality of asynchronous data signals transmitted from a plurality of channels, time-division multiplexing the plurality of asynchronous data signals in synchronization with each other, multiplexing and switching the time-division multiplexed signals, A synchronous multiplex switching circuit that outputs the obtained signals as a plurality of time division multiplexed signals, the asynchronous multiplexing and switching circuit being connected to the plurality of channels on a one-to-one basis, receiving an asynchronous data signal transmitted from the plurality of channels, and responding to a control signal. A plurality of gate means for outputting a plurality of synchronous data signals; connected to all of the plurality of gate means; storing an order for synchronously multiplexing the asynchronous data signals sent to the plurality of gate means; Control means for transmitting a signal indicating the order of the plurality of gate means to the plurality of gate means as the control signal; and A data bus for collectively outputting the plurality of synchronous data signals output from the gate means as a synchronous multiplexed data signal; receiving the synchronous multiplexed data signal supplied from the data bus; Demultiplexing means for demultiplexing and outputting the demultiplexed signal as the time division multiplexed signal. 2. The synchronous multiple exchange according to claim 1, wherein the synchronous data signals output from the plurality of gate units can be optionally multiplex exchanged by changing the order stored in the control unit. circuit.